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S70FS01GS Datasheet(PDF) 59 Page - Cypress Semiconductor

Part # S70FS01GS
Description  1-Gbit (128 MByte), 1.8 V FS-S Flash
PDF  141 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

S70FS01GS Datasheet(HTML) 59 Page - Cypress Semiconductor

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S70FS01GS
Document Number: 002-03833 Rev. *C
Page 59 of 141
The ASP register is a 16 bit OTP memory location used to permanently configure the behavior of Advanced Sector Protection (ASP)
features. ASPR does not have user programmable volatile bits, all defined bits are OTP.
The default state of the ASPR bits are programmed by Cypress.
Reserved for Future Use (RFU) ASPR[15:3]
.
Password Protection Mode Lock Bit (PWDMLB) ASPR[2]:
When programmed to 0, the Password Protection Mode is
permanently selected.
Persistent Protection Mode Lock Bit (PSTMLB) ASPR[1]:
When programmed to 0, the Persistent Protection Mode is
permanently selected. This bit may also be used in combination with the read password mode to permanently protect sectors that
would otherwise not have protection when the read password is provided. PWDMLB (ASPR[2]) and PSTMLB (ASPR[1]) are
mutually exclusive, only one may be programmed to zero.
ASPR bits may only be programmed while ASPR[2:1] = 11b. Attempting to program ASPR bits when ASPR[2:1] is not = 11b will
result in a programming error with P_ERR (SR1V[6]) set to 1. After the ASP protection mode is selected by programming ASPR[2:1]
= 10b or 01b, the state of all ASPR bits are locked and permanently protected from further programming. Attempting to program
ASPR[2:1] = 00b will result in a programming error with P_ERR (SR1V[6]) set to 1.
Similarly, OTP configuration bits listed in the ASP Register description (Section 8.4.1 ASP Register on page 67), may only be
programmed while ASPR[2:1] = 11b. The OTP configuration must be selected before selecting the ASP protection mode. The OTP
configuration bits are permanently protected from further change when the ASP protection mode is selected. Attempting to program
these OTP configuration bits when ASPR[2:1] is not = 11b will result in a programming error with P_ERR (SR1V[6]) set to 1.
The ASP protection mode should be selected during system configuration to ensure that a malicious program does not select an
undesired protection mode at a later time. By locking all the protection configuration via the ASP mode selection, later alteration of
the protection methods by malicious programs is prevented.
7.7.9
Password Register (PASS)
Related Commands: Password Read (PASSRD E7h), Read Any Register (RDAR 65h) and Write Any Register (WRAR 71h). The
PASS register is a 64 bit OTP memory location used to permanently define a password for the Advanced Sector Protection (ASP)
feature. PASS does not have user programmable volatile bits, all defined bits are OTP. A volatile copy of PASS is used to satisfy
read latency requirements but the volatile register is not user writable or further described.
Table 7.19
ASP Register (ASPR)
Bits
Field Name
Function
Type
Default
State
Description
15 to 9
RFU
Reserved
OTP
1
Reserved for Future Use
8
RFU
Reserved
OTP
1
Reserved for Future Use
7
RFU
Reserved
OTP
1
Reserved for Future Use
6
RFU
Reserved
OTP
1
Reserved for Future Use
5
RFU
Reserved
OTP
1
Reserved for Future Use
4
RFU
Reserved
OTP
1
Reserved for Future Use
3
RFU
Reserved
OTP
1
Reserved for Future Use
2
PWDMLB
Password Protection
Mode Lock Bit
OTP
1
0 = Password Protection Mode permanently enabled.
1 = Password Protection Mode not permanently enabled.
1
PSTMLB
Persistent Protection
Mode Lock Bit
OTP
1
0 = Persistent Protection Mode permanently enabled.
1 = Persistent Protection Mode not permanently enabled.
0
RFU
Reserved
OTP
1
Reserved for Future Use
Table 7.20
Password Register (PASS)
Bits
Field Name
Function
Type
Default State
Description
63 to 0
PWD
Hidden Password
OTP
FFFFFFFF-FFFFFFFFh
Non-volatile OTP storage of 64 bit password. The password is no longer
readable after the password protection mode is selected by programming
ASP register bit 2 to zero.



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