S70FS01GS datasheet(72/141 Pages) CYPRESS

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S70FS01GS

Document Number: 002-03833 Rev. *C

Page 72 of 141

operation is in progress, it is recommended to check that the Write-In Progress (WIP) bit is 0 before issuing most

commands to the device, to ensure the new command can be accepted.



Depending on the command, the time for execution varies. A command to read status information from an executing

command is available to determine when the command completes execution and whether the command was successful.



Although host software in some cases is used to directly control the SPI interface signals, the hardware interfaces of the

host system and the memory device generally handle the details of signal relationships and timing. For this reason, signal

relationships and timing are not covered in detail within this software interface focused section of the document. Instead,

the focus is on the logical sequence of bits transferred in each command rather than the signal timing and relationships.

Following are some general signal relationship descriptions to keep in mind. For additional information on the bit level

format and signal timing relationships of commands, see Section 3.2 Command Protocol on page 14.

–

The host always controls the Chip Select (CS#), Serial Clock (SCK), and Serial Input (SI) - SI for single bit wide

transfers. The memory drives Serial Output (SO) for single bit read transfers. The host and memory alternately drive

the IO0-IO3 signals during Dual and Quad transfers.

–

All commands begin with the host selecting the memory by driving CS# low before the first rising edge of SCK. CS# is

kept low throughout a command and when CS# is returned high the command ends. Generally, CS# remains low for

eight bit transfer multiples to transfer byte granularity information. Some commands will not be accepted if CS# is

returned high not at an 8 bit boundary.

9.1

Command Set Summary

9.1.1

Extended Addressing

To accommodate addressing above 128 Mb, there are two options:

1. Instructions that always require a 4-Byte address, used to access up to 32 Gb of memory:

2. A 4 Byte address mode for backward compatibility to the 3 Byte address instructions. The standard 3 Byte instructions

can be used in conjunction with a 4 Byte address mode controlled by the Address Length configuration bit (CR2V[7]). The

default value of CR2V[7] is loaded from CR2NV[7] (following power up, hardware reset, or software reset), to enable

default 3-Byte (24-bit) or 4 Byte (32 bit) addressing. When the address length (CR2V[7]) set to 1, the legacy commands

are changed to require 4-Bytes (32-bits) for the address field. The following instructions can be used in conjunction with

the 4 Byte address mode configuration to switch from 3-Bytes to 4-Bytes of address field.

Command Name

Function

Instruction (Hex)

4READ

Read

4FAST_READ

Read Fast

4DIOR

Dual I/O Read

4QIOR

Quad I/O Read

4DDRQIOR

DDR Quad I/O Read

4PP

Page Program

4P4E

Parameter 4 KB Erase

4SE

Erase 256 KB

4ECCRD

ECC Status Read

4DYBRD

DYB Read

4DYBWR

DYBWR

4PPBRD

PPB Read

4PPBP

PPB Program

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