S70FS01GS datasheet(24/141 Pages) CYPRESS

24 / 141 page

S70FS01GS

Document Number: 002-03833 Rev. *C

Page 24 of 141

4.3.3

Input Signal Overshoot

During DC conditions, input or I/O signals should remain equal to or between VSS and VDD. During voltage transitions, inputs or I/Os

may overshoot VSS to -1.0V or overshoot to VDD +1.0V, for periods up to 20 ns.

Figure 4.1

Maximum Negative Overshoot Waveform

Figure 4.2

Maximum Positive Overshoot Waveform

4.4

Power-Up and Power-Down

The device must not be selected at power-up or power-down (that is, CS# must follow the voltage applied on VDD) until VDD reaches

the correct value as follows:



VDD (min) at power-up, and then for a further delay of tPU



VSS at power-down

A simple pull-up resistor on Chip Select (CS#) can usually be used to insure safe and proper power-up and power-down.

The device ignores all instructions until a time delay of tPU has elapsed after the moment that VDD rises above the minimum VDD

threshold. See Figure 4.3. However, correct operation of the device is not guaranteed if VDD returns below VDD (min) during tPU. No

command should be sent to the device until the end of tPU.

The device draws IPOR during tPU. After power-up (tPU), the device is in Standby mode, draws CMOS standby current (ISB), and the

WEL bit is reset.

During power-down or voltage drops below VDD(cut-off), the voltage must drop below VDD(low) for a period of tPD for the part to

initialize correctly on power-up. See Figure 4.4. If during a voltage drop the VDD stays above VDD(cut-off) the part will stay initialized

and will work correctly when VDD is again above VDD(min). In the event Power-on Reset (POR) did not complete correctly after

power up, the assertion of the RESET# signal or receiving a software reset command (RESET) will restart the POR process.

Normal precautions must be taken for supply rail decoupling to stabilize the VDD supply at the device. Each device in a system

should have the VDD rail decoupled by a suitable capacitor close to the package supply connection (this capacitor is generally of the

order of 0.1µf).

Table 4.2

FS-S Power-Up / Power-Down Voltage and Timing

Symbol

Parameter

Min

Max

Unit

VDD (min)

VDD (minimum operation voltage)

1.7

VDD (cut-off)

VDD (Cut 0ff where re-initialization is needed)

1.5

VSS to VDD

- 1.0V

< = 20 ns

VDD + 1.0V

< = 20 ns

VSS to VDD

S70FS01GS Datasheet(PDF) 24 Page - Cypress Semiconductor

S70FS01GS Datasheet(HTML) 24 Page - Cypress Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL