S70FS01GS datasheet(45/141 Pages) CYPRESS

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S70FS01GS

Document Number: 002-03833 Rev. *C

Page 45 of 141

7.6

Error Correction Code (ECC)

Error Detection and Correction (EDC) is applied to all parts of the Flash address spaces other than registers. An Error Correction

Code (ECC) is calculated for each group of bytes protected and the ECC is stored in a hidden area related to the group of bytes. The

group of protected bytes and the related ECC are together called an ECC unit.



ECC is calculated for each 16 byte aligned and length ECC unit



Single Bit EDC is supported with 8 ECC bits per ECC unit, plus 1 bit for an ECC disable Flag



Sector erase resets all ECC disable flags in a sector to the default state (enabled)



ECC is programmed as part of the standard Program commands operation



ECC is disabled automatically if multiple programming operations are done on the same ECC unit.



Single byte programming or bit walking is allowed but disables ECC on the second program to the same 16 byte ECC unit.



The ECC disable flag is programmed when ECC is disabled



To re-enable ECC for an ECC unit that has been disabled, the Sector that includes the ECC unit must be erased



To ensure the best data integrity provided by EDC, each ECC unit should be programmed only once so that ECC is stored

for that unit and not disabled.



The calculation, programming, and disabling of ECC is done automatically as part of programming operations. The

detection and correction if needed is done automatically as part of read operations. The host system sees only corrected

data from a read operation.



There is a command to read the ECC status for any ECC unit.



EDC protects the OTP region - however a second program operation on the same ECC unit will disable ECC permanently

on that ECC unit (OTP is one time programmable, hence an erase operation to re-enable the ECC enable/indicator bit is

prohibited)

7.7

Registers

Registers are small groups of memory cells used to configure how the FS-S Family memory device operates or to report the status

of device operations. The registers are accessed by specific commands. The commands (and hexadecimal instruction codes) used

for each register are noted in each register description.

In legacy SPI memory devices the individual register bits could be a mixture of volatile, non-volatile, or One Time Programmable

(OTP) bits within the same register. In some configuration options the type of a register bit could change e.g. from non-volatile to

volatile.

Table 7.4

OTP Address Map

Region

Byte Address Range (Hex)

Contents

Initial Delivery State (Hex)

Region 0

000

Least Significant Byte of Cypress

Programmed Random Number

Cypress Programmed Random Number

...

00F

Most Significant Byte of Cypress

Programmed Random Number

010 to 013

Region Locking Bits

Byte 10 [bit 0] locks region 0 from

programming when = 0

...

Byte 13 [bit 7] locks region 31from

programming when = 0

All Bytes = FF

014 to 01F

Reserved for Future Use (RFU)

All Bytes = FF

Region 1

020 to 03F

Available for User Programming

All Bytes = FF

Region 2

040 to 05F

Available for User Programming

All Bytes = FF

...

Available for User Programming

All Bytes = FF

Region 31

3E0 to 3FF

Available for User Programming

All Bytes = FF

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