S70FS01GS datasheet(79/141 Pages) CYPRESS

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S70FS01GS

Document Number: 002-03833 Rev. *C

Page 79 of 141

Figure 9.4

RSFDP Command Sequence

This command is also supported in QPI mode. In Quad AIl mode the instruction is shifted in on IO0-IO3 and the returning data is

shifted out on IO0-IO3.

Figure 9.5

RSFDP QPI Mode Command Sequence

9.3

The following register access commands are not supported in the FS01GS: WRR (01h), RDCR (35h), RDSR1 (05h), RDSR2 (07h),

PNVDLR (43h). The RDAR (65h) and WRAR (71h) commands must be used for reading and writing the registers so that the

command address directs the operation to the lower or upper FS512S device in the DDP.

9.3.1

Write Enable (WREN 06h)

The Write Enable (WREN) command sets the Write Enable Latch (WEL) bit of the Status Register 1 (SR1V[1]) to a “1”. The Write

Enable Latch (WEL) bit must be set to a “1” by issuing the Write Enable (WREN) command to enable write, program and erase

commands.

CS# must be driven into the logic high state after the eighth bit of the instruction byte has been latched in on SI. Without CS# being

driven to the logic high state after the eighth bit of the instruction byte has been latched in on SI, the write enable operation will not

be executed.

Because the FS01GS is constructed from two FS512S devices stacked in a DDP, the WREN command sets the WEL bit to 1 in both

FS512S devices. Only the FS512S device that later executes a write, program, or erase command will return the WEL bit in that

device back to 0 at the end of the command execution. A Write Disable (WRDI) command must be issued to return the WEL bit to 0

in both devices. The WRDI command can be issued after each write, program, or erase command completes or once after a

sequence of such commands is completed. A WREN command is still required before each write, program, or erase command to

ensure the WEL bit is 1 before the command is executed.

Figure 9.6

Write Enable (WREN) Command Sequence

SCLK

Phase

7 6 5 4 3 2 1 0 23

1 0

7 6 5 4 3 2 1 0

Instruction

Address

Dummy Cycles

Data 1

CS#

SCK

Phase

7 6

3 2

0 23

6 5

1 0

Instruction

Address

Dummy Cycles

Data 1

CS#

SCLK

IO0

IO1

IO2

IO3

Phase

Instruct.

Address

Dummy

CS#

SCK

Phase

Instruction

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