S70FS01GS datasheet(92/141 Pages) CYPRESS

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S70FS01GS

Document Number: 002-03833 Rev. *C

Page 92 of 141

Figure 9.28

Quad I/O Read Command Sequence (4-Byte Address, ECh or EBh [CR2V[7]=1])

Figure 9.29

Quad I/O Read Command Seq. (4-Byte Address, ECh or EBh [CR2V[7]=1]) QPI Mode

9.4.5

DDR Quad I/O Read (EDh, EEh)

The DDR Quad I/O Read command improves throughput with four I/O signals - IO0-IO3. It is similar to the Quad I/O Read command

but allows input of the address four bits on every edge of the clock. In some applications, the reduced instruction overhead might

allow for code execution (XIP) directly from FS-S Family devices. The QUAD bit of the Configuration Register must be set

(CR1V[1]=1) to enable the Quad capability.

The instruction



EDh (CR2V[7]=0) is followed by a 3-byte address (A23-A0) or



EDh (CR2V[7]=1) is followed by a 4-byte address (A31-A0) or



EEh is followed by a 4-byte address (A31-A0)

The address is followed by mode bits. Then the memory contents, at the address given, is shifted out, in a DDR fashion, with four

bits at a time on each clock edge through IO0-IO3.

The maximum operating clock frequency for DDR Quad I/O Read command is 80 MHz.

For DDR Quad I/O Read, there is a latency required after the last address and mode bits are shifted into the IO0-IO3 signals before

data begins shifting out of IO0-IO3. This latency period (dummy cycles) allows the device’s internal circuitry enough time to access

the initial address. During these latency cycles, the data value on IO0-IO3 are “don’t care” and may be high impedance. When the

Data Learning Pattern (DLP) is enabled the host system must not drive the IO signals during the dummy cycles. The IO signals must

be left high impedance by the host so that the memory device can drive the DLP during the dummy cycles.

The number of dummy cycles is determined by the frequency of SCK. The latency is configured in CR2V[3:0].

For the S70FS01GS, do not enable the Continuous Read Mode, this will cause bus contention between the two 512Mb die. The

upper nibble (IO[7:4]) and lower nibble (IO[3:0]) of the Mode bits must not be complementary (i.e. 5h and Ah); this keeps the device

in the standard DDR Quad I/O read mode.

The address can start at any byte location of the memory array. The address is automatically incremented to the next higher address

in sequential order after each byte of data is shifted out. The entire memory can therefore be read out with one single read

instruction and address 000000h provided. When the highest address is reached, the address counter will wrap around and roll back

to 000000h, allowing the read sequence to be continued indefinitely.

CS#

SCK

IO0

IO1

IO2

IO3

Phase

0 28

Instruction

Address Mode

Dummy

CS#

SCLK

IO0

IO1

IO2

IO3

Phase

Instruct.

Address

Mode

Dummy

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