S70FS01GS datasheet(85/141 Pages) CYPRESS

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S70FS01GS

Document Number: 002-03833 Rev. *C

Page 85 of 141

This command is also supported in QPI mode. In Quad AIl mode the instruction is shifted in on IO0-IO3, two clock cycles per byte.

Figure 9.19

Read Any Register, QPI Mode, CR2[7] = 0, Command Sequence

Figure 9.20

Read Any Register, QPI Mode, CR2[7] = 1 Command Sequence

9.3.9

Write Any Register (WRAR 71h)

The Write Any Register (WRAR) command provides a way to write any device register - non-volatile or volatile. The instruction is

followed by a 3 or 4 Byte address (depending on the address length configuration CR2V[7], followed by one byte of data to write in

the address selected register.

The FS01GS requires that 4 Byte address mode is in use for this command so that the 4 Byte address will select the internal upper

or lower FS512S device to write. The 4BAM (B7h) command may be used to enter 4 Byte address mode before using the WRAR

command. Address A26 = 0 selects the lower address FS512S and A26 = 1 selects the higher address FS512S.

Before the WRAR command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the

device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations. The WIP bit in SR1V may be

checked to determine when the operation is completed. The P_ERR and E_ERR bits in SR1V may be checked to determine if any

error occurred during the operation.

Some registers have a mixture of bit types and individual rules controlling which bits may be modified. Some bits are read only,

some are OTP.

Read only bits are never modified and the related bits in the WRAR command data byte are ignored without setting a program or

erase error indication (P_ERR or E_ERR in SR1V). Hence, the value of these bits in the WRAR data byte do not matter.

OTP bits may only be programmed to the level opposite of their default state. Writing of OTP bits back to their default state is

ignored and no error is set.

Non-volatile bits which are changed by the WRAR data, require non-volatile register write time (tW) to be updated. The update

process involves an erase and a program operation on the non-volatile register bits. If either the erase or program portion of the

update fails the related error bit and WIP in SR1V will be set to 1.

Volatile bits which are changed by the WRAR data, require the volatile register write time (tCS) to be updated.

CS#

SCLK

IO0

IO1

IO2

IO3

Phase

Instruct.

Address

Dummy

CS#

SCLK

IO0

IO1

IO2

IO3

Phase

Instruct.

Address

Dummy

S70FS01GS Datasheet(PDF) 85 Page - Cypress Semiconductor

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