S70FS01GS datasheet(10/141 Pages) CYPRESS

10 / 141 page

S70FS01GS

Document Number: 002-03833 Rev. *C

Page 10 of 141

The WP# function is not available when the Quad mode is enabled (CR1V[1]=1). The WP# function is replaced by IO2 for input and

output during Quad mode for receiving addresses, and data to be programmed (values are latched on rising edge of the SCK signal)

as well as shifting out data (on the falling edge of SCK, in SDR commands, and on every edge of SCK, in DDR commands).

WP# has an internal pull-up resistance; when unconnected, WP# is at VIH and may be left unconnected in the host system if not

used for Quad mode or protection.

2.8

IO3 / RESET#

IO3 is used for input and output during Quad mode (CR1V[1]=1) for receiving addresses, and data to be programmed (values are

latched on rising edge of the SCK signal) as well as shifting out data (on the falling edge of SCK, in SDR commands, and on every

edge of SCK, in DDR commands).

The IO3 / RESET# signal may also be used to initiate the hardware reset function when the reset feature is enabled by writing

Configuration Register-2 non-volatile bit 5 (CR2V[5]=1). The input is only treated as RESET# when the device is not in Quad-I/O

mode, CR1V[1] = 0, or when CS# is high. When Quad I/O mode is in use, CR1V[1]=1, and the device is selected with CS# low, the

IO3 / RESET# is used only as IO3 for information transfer. When CS# is high, the IO3 / RESET# is not in use for information transfer

and is used as the RESET# input. By conditioning the reset operation on CS# high during Quad mode, the reset function remains

available during Quad mode.

When the system enters a reset condition, the CS# signal must be driven high as part of the reset process and the IO3 / RESET#

signal is driven low. When CS# goes high the IO3 / RESET# input transitions from being IO3 to being the RESET# input. The reset

condition is then detected when CS# remains high and the IO3 / RESET# signal remains low for tRP. If a reset is not intended, the

system is required to actively drive IO3 / Reset# to high along with CS# being driven high at the end of a transfer of data to the

memory. Following transfers of data to the host system, the memory will drive IO3 high during tCS. This will ensure that IO3 / Reset

is not left floating or being pulled slowly to high by the internal or an external passive pull-up. Thus, an unintended reset is not

triggered by the IO3 / RESET# not being recognized as high before the end of tRP.

The IO3 / RESET# signal is unused when the reset feature is disabled (CR2V[5]=0).

The IO3 / RESET# signal has an internal pull-up resistor and may be left unconnected in the host system if not used for Quad mode

or the reset function. The internal pull-up will hold IO3 / Reset high after the host system has actively driven the signal high and then

stops driving the signal.

Note that IO3 / Reset# cannot be shared by more than one SPI-MIO memory if any of them are operating in Quad I/O mode as IO3

being driven to or from one selected memory may look like a reset signal to a second non-selected memory sharing the same IO3 /

RESET# signal.

2.9

Voltage Supply (VDD)

VDD is the voltage source for all device internal logic. It is the single voltage used for all device internal functions including read,

program, and erase.

2.10

Supply and Signal Ground (VSS)

VSS is the common voltage drain and ground reference for the device core, input signal receivers, and output drivers.

2.11

Not Connected (NC)

No device internal signal is connected to the package connector nor is there any future plan to use the connector for a signal. The

connection may safely be used for routing space for a signal on a Printed Circuit Board (PCB).

2.12

Reserved for Future Use (RFU)

No device internal signal is currently connected to the package connector but there is potential future use of the connector. It is

recommended to not use RFU connectors for PCB routing channels so that the PCB may take advantage of future enhanced

features in compatible footprint devices.

S70FS01GS Datasheet(PDF) 10 Page - Cypress Semiconductor

S70FS01GS Datasheet(HTML) 10 Page - Cypress Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL