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Data Sheet

AD9545

Rev. A | Page 31 of 157

TERMINOLOGY

Zero Delay

Zero delay is a PLL-based clock architecture that establishes

zero phase offset between the output clock signal and input

clock signal. A zero delay architecture requires an integer-N

type PLL, by definition, because there must be a harmonic

relationship between the input and output frequencies to

preserve a static phase relationship between input and output

edges. Note that zero delay provides a zero input to output

phase offset in the static (steady state) sense only. That is,

transient events may cause the PLL to slew its output phase,

which temporarily breaks the zero delay condition (for example,

when the PLL is in the process of phase or frequency

acquisition). An example of a transient event is when a multiple

input PLL switches from one input reference signal to another.

Hitless Switchover

Hitless switchover applies to PLLs that can switch between

multiple input clock signals (usually operating at the same

frequency). Generally, the multiple input clock signals are not

phase aligned; therefore, switching from one to another can

create a substantial phase transient in the output clock signal.

Hitless switchover limits the phase transient at the output by

allowing the output clock signal to slew its phase in a prescribed

manner to accommodate the phase of the new reference signal

(typically by limiting the output frequency deviation to some

prescribed maximum value). A PLL employing hitless switchover

capability requires the output/input frequency ratio to be an

integer greater than or equal to one. Otherwise, the output

period constitutes phase in excess of 360° relative to the input

period, which creates unresolvable phase ambiguity.

Note that the output phase transient limitation imposed by

hitless switchover also applies any time the PLL is in the process

of phase or frequency acquisition (that is, it is not necessarily

limited to a reference clock switchover). A phase transient

limitation exists in hitless operation because the primary

enabler for hitless operation is the use of a narrow loop

bandwidth, which governs the transient characteristics of the

PLL in general.

Phase Buildout (PBO) Switchover

PBO switchover applies to PLLs that can switch between

multiple input clock signals (usually operating at the same

frequency). Generally, the multiple input clock signals are not

phase aligned; therefore, switching from one to another can

create a substantial phase transient in the output clock signal.

PBO capability enables the PLL to absorb the phase difference

between the original and the switched to reference clock signals,

thereby preventing a phase disturbance in the output clock

signal (unlike hitless switchover, which gradually slews the

output phase to the new input phase). Because PBO operation

prevents a disturbance in the phase of the output clock signal,

there is no guarantee of phase alignment between the input and

output clock signals. Unlike hitless switchover, PBO places no

restriction on the output/input frequency ratio.

For more information, see the AN-1420 Application Note.

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