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AD9545 Datasheet(PDF) 47 Page - Analog Devices

Part # AD9545
Description  Quad Input, 10-Output, Dual DPLL/IEEE 1588 1 pps Synchronizer and Jitter Cleaner
PDF  157 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9545 Datasheet(HTML) 47 Page - Analog Devices

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Data Sheet
AD9545
Rev. A | Page 47 of 157
REFERENCE DEMODULATOR
REFERENCE DEMODULATOR OVERVIEW
The AD9545 has four reference demodulators, one for each
reference input, REFA, REFAA, REFB, and REFBB. When
enabled, the demodulators extract embedded modulation
events from their associated input carrier clock signal. These
modulation events are essentially phase variations appearing on
the falling edge of certain input clock cycles. The primary intent
of the demodulators is to enable the detection of an embedded
clock signal originating from the output distribution of another
AD9545 (see the Distribution Embedded Output Clock
Modulation section for more detail on embedded clock
modulation).
Figure 45 shows a basic block diagram of the reference
demodulator. Although Figure 45 specifically shows the
demodulator associated with the REFA input, the diagram
applies similarly to the REFAA, REFB, and REFBB inputs. A
reference input configured for differential operation only has
access to one demodulator: Demodulator A for the REFA and
REFAA differential input and Demodulator B for the REFB and
REFBB differential input (see Figure 1).
The input clock signal at a REFx input (where x is A, AA, B, or
BB) passes through the reference receiver and drives the clock
input of the reference divider, the normal signal path when the
REFx input signal does not carry an embedded clock signal.
The output of the receiver also drives the demodulator input.
When enabled, the demodulator extracts the embedded clock
signal and uses it to synchronize the reference divider.
The demodulator expects a reference input signal containing
modulation events as described in the Distribution Embedded
Output Clock Modulation section. In general, the modulation
constitutes a lower frequency clock signal embedded within the
higher frequency carrier. The demodulator extracts the
embedded clock and the polarity of the modulation events
(optional).
The demodulated clock signal is available to the user via a
suitably configured Mx pin.
Seven control functions are associated with each demodulator
accessible via the register map, as follows:
•
Enable
•
Delay
•
Sensitivity
•
Polarity
•
Auto polarity detection
•
Persistence
•
Bandwidth
DEMODULATOR ENABLE
To enable the demodulator use the enable REFx demodulator
bit (where x is A, AA, B, or BB) in Bit D3 of Register 0x0302 to
Register 0x0303 and Register 0x0306 to Register 0x0307. Logic
0 (default) disables the demodulator, while Logic 1 enables it.
Note the demodulator requires at least an 8:1 ratio between the
frequency of the reference input and the frequency of the
embedded modulation events.
POLARITY
REFERENCE
RECEIVER
SENSITIVITY
2
2
ENABLE REFA DEMODULATOR PERSIST
ENABLE REFA DEMODULATOR POLARITY
REFA DEMODULATOR SYNC EDGE
ENABLE REFA DEMODULATOR
REFA DEMODULATOR EVENT POLARITY
REFA DEMODULATOR SENSITIVITY
REFA/AA DEMODULATOR BAND SELECT
BANDWIDTH
TO
DEMODULATOR
AA
DEMOD OUT
DEMOD IN
SYNC
AUTO POLARITY DETECT
DEMODULATOR A
POLARITY OUT
PERSISTENCE
REFERENCE
DIVIDER
REFA
ENABLE
SYNC
TO
REFA
TDC
RA
TEXT
= BIT(S) IN THE REGISTER MAP
Figure 45. Reference Demodulator



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