AD9545 datasheet(46/157 Pages) AD

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AD9545

Data Sheet

Rev. A | Page 46 of 157

begins counting down. Upon expiration of the timer, valid = 1

(see Figure 43) indicates the reference is available for use. The

valid status is via the REFx valid bit (where x is A, AA, B, or BB)

in Bit D4 of Register 0x3005 to Register 0x3008.

The user programs the validation timer period associated with

the corresponding reference via tVALID (see Figure 43). Note that

changing tVALID resets the validation timer, which invalidates a

previously valid reference but does not fault the reference

(because OOT status is unaffected by resetting the validation

timer).

It is important to note the validation timer stops counting down

whenever the reference status becomes faulted (OOT = 1, see

Figure 43). A subsequent start event causes the timer to

reinitiate a countdown from the programmed tVALID value.

Therefore, the reference does not attain valid status unless the

reference remains in tolerance for the full duration of the

validation timer.

The user has the option to force the validation timer to jump to

the end of its timing function by programming timeout = 1 (see

the Reference Monitor Controlssection and Figure 43). In this

way, if a faulted reference has returned to a nonfaulted state and

is awaiting validation, the user can override the timer if

necessary, and immediately bring the reference to a valid status.

Programming timeout = 1 has no effect on a faulted reference.

REFERENCE MONITOR RESET

The reference monitor associated with a particular reference

resets under certain conditions. A reset restarts the period

estimation process for the reference monitor. The following list

indicates the conditions that cause the reference monitor to

reset (also shown in Figure 43):

•

When the system clock status indicates unstable

•

When the user changes: the mode of the input receiver, the

R-divider value, the tREF value, the ΔtREF value, the tTOL

value, or the tHYS value

•

Optionally, when the reference experiences a significant

phase step as determined by the DPLL (assuming the user

enables phase step detection via the enable step detect

reference fault bit in Bit D7 of Register 0x2105 and

The last item requires that the user program a nonzero value in

the Profile x phase step threshold bit field. This bit field occupies a

block of consecutive register addresses with each block starting

at Address 0x080A, Address 0x082A, Address 0x084A,

Address 0x086A, Address 0x088A, Address 0x08AA, Address

0x08CA, and Address 0x08EA. See the Phase Step Limit section

for details regarding the phase step limit feature.

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