AD9545 datasheet(81/157 Pages) AD

81 / 157 page

Data Sheet

AD9545

Rev. A | Page 81 of 157

still program the Profile x.y buildout N-divider bit field to ensure

proper operation of the DPLL loop filter. Program the Profile x.y

buildout N-divider bit field as follows (refer to Figure 65):

NBUILDOUT

= round((2 × Q × R1 × fOUTx)/(M × fREFx1))

where:

round() is a function to round the quantity in () to the nearest

integer, assuming the quantity is within the range of the Profile x.y

buildout N-divider bit field.

Q is the Q divider.

M is the M divider (see Figure 62).

DPLL LOOP FILTER

DPLL0 and DPLL1 make use of a digital IIR filter loop filter.

The digital filter is analogous to the third-order analog filter

shown in Figure 69, where input is on the left (from the phase

detector) and output is on the right (to the VCO).

Figure 69. Third-Order Analog Loop Filter

Whereas the response of an analog loop filter is a function of

physical components subject to thermal drift and aging, the

response of a digital loop is a function of numeric coefficients

and is not subject to thermal drift and aging. Figure 70 is a

block diagram showing the digital loop filters and their control

elements.

For completeness, Figure 70 shows the fast acquisition control

block of the AD9545 as part of the loop filter control because

the fast acquisition feature dynamically adjusts the loop

bandwidth as part of the fast acquisition process (see the DPLL

Fast Acquisition (FACQ) Options section).

Generally, the response characteristics of a digital filter depend

solely on the numeric coefficients. However, the DPLL loop

filters are special in that they require additional input, namely, a

bandwidth scale factor and the numeric value of the DPLL

feedback divider (see the DPLL Feedback Divider (N-Divider)

section for details). The DPLL automatically resets the internal

state of the loop filter when the loop is not active (for example,

entry into holdover or freerun mode).

DIGITAL

LOOP

FILTER

DPLL0

FROM

DIGITAL PFD

NCO

LOOP

FILTER

COEFFICIENTS

PROFILE 0.x LOOP FILTER BASE

FAST

ACQ0

PHASE LOCK

DETECT

LOOP FILTER 0

COEFFICIENTS

ADJ

DIGITAL

LOOP

FILTER

DPLL1

FROM

DIGITAL PFD

NCO

LOOP

FILTER

COEFFICIENTS

PHASE LOCK

DETECT

TEXT

= BIT(S) IN THE REGISTER MAP

LOOP FILTER 1

COEFFICIENTS

LF0

LF1

PROFILE 0.x

BUILDOUT

N-DIVIDER

PROFILE 0.x LOOP BANDWIDTH

PROFILE 1.x LOOP FILTER BASE

ADJ

PROFILE 1.x LOOP BANDWIDTH

x = TRANSLATION PROFILE (0 TO 5)

FAST

ACQ 1

PROFILE 1.x

BUILDOUT

N-DIVIDER

Figure 70. Digital Loop Filter Block Diagram

AD9545 Datasheet(PDF) 81 Page - Analog Devices

AD9545 Datasheet(HTML) 81 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL