AD9545 datasheet(38/157 Pages) AD

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AD9545

Data Sheet

Rev. A | Page 38 of 157

SYSTEM CLOCK STABILITY COMPENSATION

An application requiring low DPLL loop bandwidth necessitates

the use of a very stable system clock source. Using a relatively

unstable system clock source like a crystal resonator or crystal

oscillator, for example, in conjunction with the DPLL having a

very narrow loop bandwidth (below approximately 50 Hz) may

cause the DPLL to unlock or experience intermittent unlock

events. The classic solution requires the use of a very stable

system clock source (an OCXO, for example). An alternate

solution uses the integrated system clock compensation of the

AD9545, which enables the use of a crystal resonator as the

system clock source. The basic concept is the connection of a

crystal resonator (25 MHz to 60 MHz) to the XOA and XOB

pins per Figure 23, which capitalizes on the exceptional phase

noise performance of the crystal.

However, the crystal resonator lacks the desired stability. Instead,

the stability arises via the connection of a highly stable source

(for example, TCXO, OCXO, and GPS) to an unused REFx or

Mx input.

The stable source is the reference input to one of the DPLL

channels, which enables the internal timing system in the

AD9545 to benefit from both the stability of the highly stable

source and the exceptional phase noise performance of the

crystal resonator. This combination enables the AD9545 to

apply system clock compensation to the second DPLL channel,

thereby allowing that channel to use the low loop bandwidth

required by the application.

AD9545 Datasheet(PDF) 38 Page - Analog Devices