AD9545 datasheet(67/157 Pages) AD

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Data Sheet

AD9545

Rev. A | Page 67 of 157

Because the SNCx signal identifies the modulation base edge,

the user can synchronize the DPLL N-divider with a specific

sync edge per Figure 60. To specify a sync edge for the N-divider

use the 2-bit unsigned feedback divider sync edge bit field in

Bits[D1:D0] of Register 0x10CE and Register 0x14CE. The

value of the feedback divider sync edge bit field (0, 1, 2, or 3)

corresponds to the desired sync edge in Figure 60.

There is an additional constraint on the value of Qxy

modulation counter (see the Modulation Period section) when

using the Q divider in the DPLL feedback path. The constraint

relates to the value of Feedback divider sync edge as follows:

Qxy Modulation Counter ≥ Feedback Divider Sync Edge + 7

MODULATION TRIGGER

By default, when modulation is in effect for a given Q divider,

the modulator applies the modulation immediately. However, it

is also possible to delay modulation until triggered. Enable this

feature for a particular modulator via the enable Qxy N-shot

modulator bit (where x is 0 or 1 and y is A, B, or C) in Bit D3 of

feature, whereas Logic 1 enables it.

When enabled, the modulators use the trigger and mode signals

originating within the N-shot/PRBS controller (see Figure 48).

The mode behavior differs slightly from that of the N-

shot/PRBS controller. Specifically, when N-shot request mode =

0, instead of the modulator continuously generating periodic

modulation events, it generates only five periodic modulation

events and then stops. Conversely, when N-shot request mode =

1, the modulator continuously generates modulation events

when the N-shot request signal (see Figure 48) is Logic 1. This

behavior allows synchronous enable/disable of modulation

events without losing synchronization during modulation.

Q0A

Q0AA

Q0B

TRIGGER

SIGNAL

RETIMED

TRIGGER

N-SHOT OUT0AP

N-SHOT OUT0AN

N-SHOT OUT0BP

TIME

3 OUTPUT CYCLE LATENCY

MINIMUM 48 Q-DIVIDER INPUT HALF CYCLES

Figure 61. Trigger Retiming (with Q0AA as the Retiming Q Divider)

AD9545 Datasheet(PDF) 67 Page - Analog Devices

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