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AD9545

Data Sheet

Rev. A | Page 70 of 157

FREQUENCY TRANSLATION LOOPS

FREQUENCY TRANSLATION LOOPS OVERVIEW

The frequency translation capability of the AD9545 comprises

two independent dual PLL channels (Channel 0 and Channel 1).

Each PLL channel comprises a digital PLL (DPLL) followed by

an analog PLL (APLL). Both channels have programmable

reference dividers at the input and programmable channel

dividers at the output. A block diagram of a single channel

appears in Figure 62.

The DPLL channels (DPLL0 and DPLL1) are capable of very

low loop bandwidths (µHz) well suited for jitter cleanup

applications involving the 1 pulse per second (pps) input signals

that originate from GPS and GNSS receivers. The DPLL is of

the fractional-N variety, but is capable of integer-N operation

when the fractional part is set to zero.

The DPLL provides an output frequency of up to approximately

400 MHz. The DPLL also plays a role in the automatic reference

switching capability of the AD9545 and its ability to provide

hitless and phase buildout functionality.

The APLL is of the integer-N variety with an integrated VCO

and provides the high frequency upconversion capability of the

cascaded DPLL/APLL pair. Unlike the two DPLLs, which are

identical, the two APLLs differ slightly. Specifically, they have

nonoverlapping VCO ranges with APLL0 spanning 2.424 GHz

to 3.232 GHz and APLL1 spanning 3.232 GHz to 4.04 GHz.

TRANSLATION PROFILES

DPLL0 and DPLL1 each have six dedicated sections in the

Profile 0.0 through Translation Profile 0.5 for DPLL0 and

Translation Profile 1.0 through Translation Profile 1.5 for

DPLL1). Each translation profile consists of the following

programmable parameters:

•

Profile enable

•

Profile priority

•

Translation mode selection

•

Input reference source selection

•

N-divider value (integer, fraction, and modulus)

•

DPLL loop filter

•

Reference and feedback TDC tagging options

•

DPLL fast acquisition (FACQ) options

When a particular profile is in effect, the DPLL uses the

parameters as specified in that profile. That is, the DPLL has no

memory with regard to switching between profiles.

The translation profiles control only the frequency translation

of the DPLL. The overall frequency translation of the channel

depends on the following:

•

N-divider value (depending on the translation mode)

•

M-divider value (via the APLL0 and APLL1 controls)

•

R-divider value (via the REFx controls)

•

Q divider value (via the distribution controls).

Each divider type has a dedicated section in this data sheet with

detailed information on the use and programming of the

divider values.

REFx

REFy

TDC

INTERNAL ZERO-DELAY

OUTxyN/

OUTxyP

REFX

TDC

EXTERNAL ZERO DELAY

MAY INCLUDE ADDITIONAL FREQUENCY TRANSLATION

AD9545

REFY

TDC

AUX

NCO 0/NCO 1

TDC

OTHER DPLL

FEEDBACK

TDC

DIGITAL CROSS

POINT MUX

TIME STAMP PROCESSOR,

DIGITAL LOOP FILTER,

TUNING WORD PROCESSOR

AND NCO

FEEDBACK

TDC

PFD

AND

LOOP

FILTER

N-DIVIDER

TDC

OUTPUT

DISTRIBUTION

PHASE

BUILD

OUT

DPLL

N + FRAC/MOD

MUX

SYSTEM

CLOCK

LFx

XOA XOB

APLL

VCO

Figure 62. Frequency Translation Loop Block Diagram

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