AD9545 datasheet(37/157 Pages) AD

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Data Sheet

AD9545

Rev. A | Page 37 of 157

voltage swing is 800 mV p-p). The external signal must exhibit a

50% duty cycle for best performance.

2× FREQUENCY MULTIPLIER

The system clock PLL provides the user with the option of

doubling the reference frequency via the enable SYSCLK

doubler bit in Bit D0 of Register 0x0201. Programming Logic 1

doubles the input reference frequency, which potentially

reduces the PLL in band noise. Note the reference frequency must

be less than 150 MHz when using the 2× frequency multiplier to

satisfy the 300 MHz maximum PFD rate. The 2× frequency

multiplier requires the reference input signal to have very near to

50% duty cycle; otherwise, the resulting spurious content may

prevent the system clock PLL from locking.

PRESCALE DIVIDER

The system clock PLL includes an input prescale divider

programmable for divide ratios of 1 (default), 2, 4, or 8. The

purpose of the divider provides flexible frequency planning for

mitigating potential spurs in the output clock signals of the

AD9545. The user selects the divide ratio via the 2-bit SYSCLK

input divider ratio bit field in Bits[D2:D1] of Register 0x0201.

The corresponding divide value is 2J, where J is the decimal value

of the 2-bit number in the SYSCLK input divider ratio bit field.

For example, given a SYSCLK input divider ratio bit field value

of 10 (binary) and J = 2 (decimal) yields a divide ratio of

2J = 22 = 4.

FEEDBACK DIVIDER

The output of the system clock PLL constitutes the system clock

frequency, fS. The system clock frequency depends on the value of

the feedback divider (K in Figure 41). The feedback divide ratio has

a range of 4 to 255, which the user programs via the 8-bit feedback

divider ratio register (Register 0x0200). The programmed register

value is the divide ratio. For example, a programmed value of 100

(0x64 hexadecimal) yields a divide ratio of 100.

SYSTEM CLOCK PLL OUTPUT FREQUENCY

Calculate the system clock frequency as follows:

= fOSC ×

where:

fOSC

is the input frequency.

K is the feedback divide ratio.

J is the input divide ratio. J = ½ when using the 2× frequency

multiplier.

The user must choose fOSC, K, and J such that fS satisfies the

VCO range of 2250 MHz to 2415 MHz.

SYSTEM CLOCK PLL LOCK DETECTOR

The system clock PLL features a simple lock detector that

compares the time difference between the reference and

feedback clock edges. The user can check the status of the lock

detector via the SYSCLK locked bit in Bit D0 of Register

0x3001, where Logic 1 indicates locked and Logic 0 unlocked.

The most common reason the system clock PLL fails to lock is

due to the user employing the 2× frequency multiplier with a

reference input clock that deviates from the 50% duty cycle.

SYSTEM CLOCK STABILITY TIMER

Because time processing blocks within the AD9545 depend on

the system clock generating a stable frequency, the system clock

PLL provides an indication of its status. The status of the system

clock PLL is available to the user as well as directly to certain

internal time keeping blocks.

At initial power-up, the system clock status is unknown and

reported as being unstable. However, after the user programs

the system clock registers and the system clock PLL VCO

calibrates, the system clock PLL locks shortly thereafter.

Even though the system clock PLL may indicate lock status, the

user can introduce an additional hold off period via the unsigned

20-bit system clock stability period bit field in Register 0x0207

to Register 0x0209. The system clock stability period bit field

constitutes units of milli-seconds (10−3 sec). Note there are two

special values: 0 and 1,048,575. A value of 0 causes the system

clock to indicate unstable status regardless of the actual state of

the system clock (useful for debugging purposes, because the

user can force an unstable status indication even though the

PLL is stable). A value of 1,048,575 is invalid because it causes

the SYSCLK stable bit (Register 0x3001, Bit D1) to be undefined

when the system clock PLL is unlocked.

SYSTEM CLOCK CALIBRATION

The VCO in the system clock PLL requires a calibration

sequence. At power-up, part of the initialization sequence of the

device includes system clock calibration. In general, the user is

not required to calibrate the system clock manually.

However, changing any of the system clock parameters that

result in a new VCO frequency requires a manual system clock

calibration. To do so, use the calibrate SYSCLK bit in Bit D2 of

bit; thus, the full programming sequence involves writing Logic 1

followed by an IO_UPDATE operation, and then writing Logic 0

followed by another IO_UPDATE operation. Furthermore,

whenever the system clock PLL is in the process of calibrating,

the device asserts the SYSCLK calibration busy bit in Bit D2 of

Although the AD9545 has a variety of power-down modes,

including a specific system clock power-down, it is not

necessary to calibrate the system clock when recovering from

any of the power-down modes. However, recovering from a

power-down of the system clock necessitates calibration of the

APLLs due to the loss of the system clock during its power-down.

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