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Data Sheet

AD9545

Rev. A | Page 53 of 157

DISTRIBUTION DIVIDERS (Q DIVIDERS)

DISTRIBUTION DIVIDERS OVERVIEW

There are five pairs of Q dividers corresponding to the five pairs

of clock output drivers (see the Distribution Clock Output

Drivers section). Unlike typical clock dividers, which count the

rising edge (or falling edge) of its input clock, the Q dividers

count both the rising and falling edges of its input clock. Dual-

edge counting enables features not possible with a typical

counter.

The Q dividers respond to several controllers, which implement

the various features of the Q dividers. Figure 47 shows a

diagram of the Q dividers and associated controllers. Although

not explicitly shown, the output of each Q divider routes to its

corresponding output driver.

Each Q divider has independent phase offset (delay) capability

as governed by a phase offset controller (see the Distribution

Phase Offset Control section). In addition, a sophisticated and

flexible synchronization mechanism provides synchronized

output clock timing for any or all Q divider output signals (see

the Distribution Output Clock Synchronization section). A

JESD204B and burst controller enables each Q divider to

generate a clock signal supporting JESD204B or to generate

flexible burst patterns supporting gapped clock and similar

applications (see the Distribution N-Shot/PRBS Output

Clocking section).

Furthermore, the Qxy divider of each Q divider pair is capable

of modulating the location of the falling edges of the output

clock signal. The modulation of the clock edge location

supports embedded clock applications such as transporting a

lower frequency clock signal over a higher frequency carrier

clock (see the Distribution Embedded Output Clock

Modulation section).

At power-up, the synchronization controller holds the disabled

Q dividers (that is, there are no output clocks). Consequently,

the user must issue a sync request (see the Distribution Output

Clock Synchronization section following a power-up or reset to

initialize the Q dividers.

Q DIVIDER CLOCK SOURCE SELECTION

Each pair of Q dividers shares a common clock input (see

Figure 47) that originate from one of two sources:

•

From the output of the associated APLL channel of the

Q divider.

•

From the system clock divided by three (~800 MHz).

The first source is the normal (default) operating mode, which

provides frequency translation from a reference input to the

distribution output via the corresponding PLL channel. The

second source is the output frequency of the system clock PLL

divided by three, which is useful for clocking certain peripheral

devices (a microprocessor, for example). In this scenario, the

user can employ an optional external EEPROM to download a

device configuration that provides an output clock signal at

power up via the system clock source path (see the EEPROM

Usage section).

The enable SYSCLK Qxy bits (where x is 0 or 1 and y is A, B, or

C) in Bits[D3:D1] of Register 0x10DA and Register 0x14DA

select the Q divider clock source for each Q divider pair. Logic 0

(default) selects the output of the corresponding APLL as the

Q divider clock source, whereas Logic 1 selects the output of the

system clock PLL as the Q divider clock source.

When the AD9545 is configured with the system clock as the

clock source for a Q divider pair, use the enable SYSCLK sync

mask bit in Bit D0 of Register 0x10DA and Register 0x14DA to

prevent those particular dividers from being resynchronized

every time a sync trigger occurs (see the Distribution Output

Clock Synchronization section). When this bit is set, any of the

Q dividers associated with a particular PLL channel and having

the system clock as their clock source are immune to

synchronization events. This feature is particularly useful for

outputs that serve as the clock source to a microprocessor, for

example, because an unmasked synchronization event disrupts

the clock signal of the processor.

In some applications, when more than one Q divider pair uses

the system clock as its clock source, it may be desirable to

synchronize at least two of those Q divider pairs. To do so,

initiate a synchronization sequence (see the Distribution

Output Clock Synchronization section), then assert the enable

SYSCLK sync mask bit. To reconfigure the affected Q dividers

by changing the divide ratio, for example, the user must first

clear the enable SYSCLK sync mask bit.

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