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AD9545

Data Sheet

Rev. A | Page 64 of 157

TIME

NOMINAL

(50%)

Δt

MODULATION PERIOD (PM)

NOMINAL

(50%)

MODULATION MAGNITUDE

(D =

Δt/PQ)

Q DIVIDER

OUTPUT PERIOD (PQ)

Figure 55. Modulation Magnitude and Period

Modulation control consists of two parameters: Δt and PM.

Parameter Δt defines the desired magnitude of the modulation

edge variation, and PM defines the modulation period (see

Figure 55). The modulated signal consists of a time step of

magnitude Δt occurring at regular intervals of period, PM. The

magnitude parameter, Δt, is common to all the modulators

within a PLL channel, whereas the period parameter, PM, is

unique to each modulator.

MODULATION MAGNITUDE

To set the modulation magnitude use the 16-bit unsigned

Modulation step bit field in Register 0x10C0 to Register 0x10C1

and Register 0x14C0 to Register 0x14C1. The units associated

with the modulation step bit field are one-half of the period of

the input clock to the Q divider associated with the modulator,

yielding the following relationship:

D = Modulation step/(2 × Qxy)

(3)

where:

D is the duty cycle deviation (that is, the time deviation of the

modulation edge from nominal, normalized to the Q divider

output period). Figure 55 shows D as Δt/PQ.

Qxy is the divide ratio of the relevant Q divider (x is 0 or 1 and y

is A, B or C).

Because the modulation step bit field is common to all the

modulators in a PLL channel, whereas Qxy is unique to each

Q divider, D in Equation 3 is not necessarily the same for all the

modulators in a PLL channel.

Given the divide ratio for Q Divider Q0A is 1001, find the

modulation step bit field value necessary for Modulator A to

yield 5% modulation.

Modulation of 5% implies D = 0.05. Substituting the

appropriate values into Equation 3 yields

0.05 = Modulation step/(2 × 1001),

Therefore,

Modulation step = 100 (rounded to nearest integer)

= 0x64 (hexadecimal)

Given the same modulation step value as in the prececing

example (modulation step = 100), find the modulation magnitude

for Modulator B assuming Q0B has a divide ratio of 8025.5.

D = modulation step/(2 × Qxy)

= 100/(2 × 8025.5)

= 0.00623 (0.623%)

MODULATION PERIOD

The modulation period is the interval between modulation

events (see Figure 55). To control the modulation period

parameter, use the 28-bit unsigned Qxy modulation counter bit

field (where x is 0 or 1 and y is A, B or C) in Register 0x10C2 to

units associated with the Qxy modulation counter bit field is the

period of the output clock of the associated Q divider.

The Qxy modulation counter bit field has a constraint on its

minimum value:

Qxy modulation counter ≥ 6

The modulation period (PM) depends on the input clock

frequency (fIN), the divide ratio (Qxy_DIV) of the associated Q

divider and the value of the Qxy modulation counter bit field.

PM = Qxy modulation counter × (Qxy/fIN)

(4)

Suppose the input clock to Q Divider Q0A comes from APLL0

with its VCO operating at 2.38 GHz. Because the VCO drives

a divide-by-2 block prior to the Q divider clock input, the

Q divider input frequency (fIN) is 1.19 GHz. Find the value of

the Qxy modulation counter bit field required to yield a

modulation period (PM) of 1 ms (0.001 sec) for a Q divide ratio

(Qxy_DIV) of 107.5.

Substituting the appropriate values into Equation 4 yields

10−3 = Qxy modulation counter × (107.5/(1.19 × 109)),

Therefore,

Qxy modulation counter = 11,070 (nearest integer)

= 0x00002B3E (hexadecimal)

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