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AD9545

Data Sheet

Rev. A | Page 54 of 157

MODULATION

QXY

SYNC

QXYY

SYSTEM

CLOCK

PLL0/PLL1

P-DIVIDER

Q-DIVIDER PAIR 1

Q-DIVIDER PAIR 5

OUTPUT

DRIVERS

N-SHOT/PRBS

CONTROLLER

PHASE OFFSET

CONTROLLER

SYNCHRONIZATION

CONTROLLER

TO Q-DIVIDER PAIRS 2 TO 5

MODULATION

CONTROLLER

N-SHOT/PRBS

PHASE OFFSET

SYNC

Figure 47. Functional Block Diagram of Q Dividers and Controllers

INTEGER DIVISION

The Q divider divide ratio (Q) depends on the 32-bit unsigned

Qxy divider ratio bit fields (where x is the channel (0 or 1) and y

is the Q divider (A, AA, B, BB, C, or CC)) in registers starting

with Address 0x1100, Address 0x1109, Address 0x1112,

Address 0x111B, Address 0x1124, Address 0x112D, Address

0x1500, Address 0x1509, Address 0x1512, and Address 0x151B.

There are 10 occurrences of this bit field, one for each Q divider.

To program the divide ratio, write the value of Q into the

corresponding Qxy divider ratio bit field and then set the

IO_UPDATE bit. The range of the Q divider is 1 to

4,294,967,295.

For example, for a desired divide ratio of Q = 1,000,000. The

required bit field value is 1,000,000 (0x000F4240 hexadecimal).

A value of 0 (default) sets a divide ratio of 1, which is an

unsupported divide ratio. Therefore, at power-up or after

resetting the device, the user must program the Qxy divider

ratio bit fields with values greater than 1 to enable the

corresponding Q dividers.

Although it is possible to program a different divide ratio for

each Q divider of a Q divider pair, the recommendation is to

avoid doing so because a Q divider pair with differing divide

ratios results in two different output frequencies and can cause

cross coupling issues (due to the close physical proximity of the

corresponding output drivers). The intent is for Q divider pairs

to operate with the same output frequency but with the option

to control the relative phase between the outputs (see the

Distribution Phase Offset Control section).

HALF INTEGER DIVISION

The Q dividers are unique in that they support half integer

division, a benefit of the Q dividers counting both the rising

and falling edges of the input clock. To enable half integer

division for the corresponding Q divider, use the enable Qxy

half divide bit (where x is the 0 or 1 and y is the A, AA, B, BB, C,

or CC).

The enable Qxy half divide bit resides in Bit D5 of

When the enable Qxy half divide bit is Logic 1, it effectively

adds an extra 0.5 to the divide ratio prescribed by the

corresponding 32-bit Qxy divider ratio bit field. The value of

the enable Qxy half divide bit does not become effective until

the user sets the IO_UPDATE bit.

For example, assume the Qxy divider ratio bit field equals 100.

If the associated enable Qxy half divide bit is Logic 1, the total

divide ratio is 100.5.

Q DIVIDER RESET

Each Q divider has a dedicated reset bit, reset Qxy (where x is 0

or 1 and y is A, AA, B, BB, C, or CC in D1 of Register 0x2102 to

reset Qxy bits allow the user to reset the Q dividers manually in

applications that do not require output clock synchronization.

In most cases, however, there is no need to set these bits during

normal operation because the synchronization controller

automatically handles the Q divider reset function (see the

Distribution Output Clock Synchronization section).

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