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AD9545

Data Sheet

Rev. A | Page 16 of 157

HOLDOVER SPECIFICATIONS

Table 12.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

HOLDOVER SPECIFICATIONS

Initial Frequency Accuracy

±0.01

±0.1

ppb

AD9545 is configured using Configuration 1 from Table 22;

excludes frequency drift of system clock (SYSCLK) source;

excludes frequency drift of input reference prior to

entering holdover; 160 ms history timer; history hold off

setting of 8; three features (bits) are enabled: DPLLx delay

history frequency lock (Bit 4 in Register 0x100E and

history until not slew limiting (Bit 5 in Register 0x100E and

Relative Frequency Accuracy

Between Channels

Cascaded Operation

ppb

History Averaging Window

0.001

268435

sec

ANALOG PLL (APLL0, APLL1) SPECIFICATIONS

Table 13.

Parameter

Min

Typ

Max

Unit

VCO FREQUENCY RANGE

Analog PLL0 (APLL0)

2424

3232

MHz

Analog PLL1 (APLL1)

3232

4040

MHz

PHASE FREQUENCY DETECTOR (PFD) INPUT FREQUENCY RANGE

162

350

MHz

LOOP BANDWIDTH

260

kHz

PHASE MARGIN

Degrees

OUTPUT CHANNEL DIVIDER SPECIFICATIONS

Table 14.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

OUTPUT PHASE ADJUST STEP SIZE

tVCO

tVCO = 1/(APLLx VCO frequency), where x = 0, 1

MODULATOR

Carrier Frequency

fVCO ÷ 16

The maximum value is the APLL0/1 VCO frequency divided by 16

Time Deviation (from Nominal

Duty Cycle of Carrier Clock)

216 − 1

tVCO

tVCO = 1/(APLLx VCO frequency), where x = 0, 1; the maximum

value is limited to the Qxy divide ratio − 1; Qxy refers to the

distribution dividers on each output, where x is either 0 (for

PLL0) or 1 (for PLL1), and y is A, B, or C

Embedded Frequency

fOUT ÷ (228 − 1)

fOUT ÷ 6

fOUT is the output frequency

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