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Data Sheet

AD9545

Rev. A | Page 95 of 157

Programming Delay Compensation Coefficients (Cx)

Coefficient C1 through C5 apply scale factors to the appropriate

powers of T. The Cx coefficients carry units of seconds/(°Cx).

The user programs the C1 through C5 coefficients via the signed

(twos complement) 16-bit DPLLx phase temperature compensa-

tion Ck significand and signed (twos complement) 8-bit DPLLx

phase temperature compensation Cx exponent bit fields, where

x (where x is 0 or 1). The Cx coefficients reside in Register 0x101A

to Register 0x1028 and Register 0x141A to Register 0x1428.

The Cx coefficient bit fields (DPLLx phase temperature

compensation Cx significand and DPLLx phase temperature

compensation Cx exponent) program in exactly the same

manner as the Tx significand and Tx exponent bit fields in the

System Clock Compensation section of the register map. An

example follows (see the Compensation Method 1 section for

details on converting coefficient values to bit field values).

Suppose a user makes measurements that indicate the output

clock signals of the AD9545 exhibit a delay variation of

−1 ns/°C. To compensate for this variation, apply a 1 ns/°C

correction. In polynomial form,

f(T) = C5T5 + C4T4 + C3T3 + C2T2 + C1T

where f(T) is the correction value in units of seconds as a

function of temperature (T).

Because the delay variation in this example is strictly linear with

respect to temperature, all the coefficients are zero except for

C1. Thus, in this example, the compensation polynomial

simplifies to the following:

f(T) = C1T

To apply 1 ns/°C compensation, C1 = 10−9 sec/°C. Referring to

the procedure in the Compensation Method 1 section, obtain

the following bit field values for C1:

C1_ExpVal =

log













log

-9













= −29

This value is greater than the quantization limit of −127.

Therefore, for the DPLLx phase temperature compensation

(PTC) C1 exponent,

DPLLx PTC C1 Exponent = C1_ExpVal

= −29

= 0xE3 (hexadecimal)

For the DPLLx PTC C1 significand,

DPLLx PTC C1 significand = C1 × 215 − C1_ExpVal

= 10−9 × 215 − (−29)

= 17,592 (nearest integer)

= 0x44B8 (hexadecimal)

Delay Compensation Filter

The Δt values produced by the delay compensation block depend

on temperature measurements (internal or external) as an input

parameter. Any noise associated with those measurements is a

potential noise source on Δt, which can lead to a degradation of

the phase noise performance of the DPLL. To mitigate potential

noise injection, the delay compensation block uses a filter that

applies a smoothing function to the raw Δt values.

The phase slew limiter (see the Phase Slew Rate Limit section)

does not process time variations injected into the DPLL by the

delay compensation filter. That is, these variations affect the

DPLL output without intervention by the phase slew limiter.

The user controls the filter bandwidth via the 3-bit unsigned

DPLLx phase temperature compensation filter bandwidth bit

field (where x is 0 or 1) in Bits[D2:D0] of Register 0x1029 and

yielding a 3 dB bandwidth per Table 45 (which also shows the

transition time to 99% of a step input, associated with a step

change at the input to the filter).

Table 45. Delay Compensation Filter Bandwidth

Binary Value

3 dB Bandwidth (Hz)

Transition Time (ms)

000

243

3.27

001

121

6.58

010

13.0

011

26.5

100

53.1

101

99.5

110

199

111

398

TIME STAMP TAGGING OPTIONS

The input to the DPLL constitutes a reference TDC source and

a feedback TDC source. Furthermore, the user can enable

tagging of time stamps originating from those TDCs (see the

Tagged Time Stamps section). The user can also enable the

DPLL to operate based on tagged time stamps originating from

the reference and/or feedback TDCs.

The use of tagged timestamps by the DPLL only applies for zero

delay (hitless) mode. The DPLL ignores tagged time stamps in

phase buildout mode. See the Frequency Translation Loops section

for an explanation of zero delay and phase buildout modes.

The user establishes the tagged time stamp functionality of the

DPLL via the Profile x.y tag mode bit field in Bits[D4:D2] of

0x1623, Register 0x1643, Register 0x1663, Register 0x1683, and

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