AD9545 datasheet(10/157 Pages) AD

10 / 157 page

AD9545

Data Sheet

Rev. A | Page 10 of 157

SYSTEM CLOCK INPUTS, XOA AND XOB

Table 4.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SYSTEM CLOCK MULTIPLIER

Output Frequency Range

2250

2415

MHz

The frequency range of the internal voltage controlled

oscillator (VCO) places limits on the choice of the system

clock input frequency

Phase Frequency Detector (PFD) Rate

300

MHz

SYSTEM CLOCK REFERENCE INPUT PATH

System clock input must be ac-coupled

Input Frequency Range

System Clock Input Doubler

Disabled

300

MHz

Support of oven controlled crystal oscillators (OCXOs)

< 20 MHz is possible using the auxiliary DPLL for system

clock frequency compensation

Enabled

150

MHz

Self Biased Common-Mode Voltage

0.75

Internally generated

Input Voltage

For dc-coupled, single-ended operation

High

0.9

Low

0.5

Differential Input Voltage Sensitivity

250

mV p-p

Minimum voltage swing required (as measured with a

differential probe) across the XOA/XOB pins to ensure

switching between logic states; the instantaneous voltage on

either pin must not exceed 1.2 V; accommodate the single-

ended input by ac grounding the complementary input;

800 mV p-p recommended for optimal jitter performance

Slew Rate for Sinusoidal Input

V/µs

Minimum input slew rate for device operation; oscillators

with square wave outputs are recommended if not using a

crystal

System Clock Input Divider

(J Divider) Frequency

100

MHz

System Clock Input Doubler

Duty Cycle

Tolerable duty cycle variation on the system clock input

when using the frequency doubler

20 MHz to 150 MHz

16 MHz to 20 MHz

Input Resistance

kΩ

QUARTZ CRYSTAL RESONATOR PATH

Resonator Frequency Range

MHz

Fundamental mode, AT cut crystal

Maximum Crystal Motional Resistance

100

Ω

A maximum motional resistance of 50 Ω, and maximum

CLOAD of 8 pF is strongly recommended for crystals >52 MHz

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