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AD9545 Datasheet(PDF) 34 Page - Analog Devices |
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AD9545 Datasheet(HTML) 34 Page - Analog Devices |
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34 / 157 page  AD9545 Data Sheet Rev. A | Page 34 of 157 CLOCK OUTPUTS AD9545 I I PLLx +1.8V QXY QXYY ISOURCE MODE OUTxyP OUTxyN 50 Ω 100 Ω 50 Ω 0.1µF 0.1µF LVDS OR LVPECL RECEIVER LVDS: USE 7.5mA DRIVER SETTING. LVPECL: USE 15mA DRIVER SETTING. Figure 31. LVDS-Compatible Output Swing, AC-Coupled (V p-p ≈ 375 mV per Section for I = 15 mA) The output drivers of the AD9545 are capable of either sourcing or sinking current. Each pin of an output pin pair (OUTxyP/ OUTxyN) has an independent current source. However, the source or sink function applies to both current sources of an output pin pair (that is, either both pin drivers source current (ISOURCE)or both pin drivers sink current (ISINK)). The current source (sink) of the individual driver is either on or off depending on the logic level of the associated Qxy or Qxyy divider (0 = off, 1 = on). The Qxy divider has both normal and inverted logic outputs, which means when the Qxy divider is connected to both output drivers (as in Figure 31, for example), one current source is on while the other is off, allowing a differential output signal. See the Distribution Clock Output Drivers section for configuring the clock output drivers. AD9545 I I PLLx +1.8V QXY QXYY ISOURCE MODE OUTxyP OUTxyN 50 Ω 50 Ω TO HCSL RECEIVER Figure 32. HCSL Output, V p-p ≈ 750 mV per Section (I = 15 mA) AD9545 I I PLLx QXY QXYY ISINK MODE OUTxyP OUTxyN 50 Ω 50 Ω 1.2V, 1.5V OR 1.8V Figure 33. CML Output (I = 7.5 mA; I = 15 mA Options for 1.5 V or 1.8 V Supply) AD9545 I I PLLx QXY QXYY ISINK MODE OUTxyP OUTxyN 50 Ω 50 Ω 50 Ω 1.8V 10nF RL Figure 34. LVDS-Compatible Output, 1.24 V Common Mode, T Network (I = 7.5 mA; I = 15 mA with Extra 100 Ω Termination, RL) AD9545 I I PLLx QXY QXYY ISINK MODE OUTxyP OUTxyN 1.8V RL 63.4 Ω 237Ω 63.4 Ω 237Ω Figure 35. LVDS-Compatible Output, 1.2 V Common-Mode, Thevenin Bias Network (I = 7.5 mA; 15 mA with Extra 100 Ω Termination, RL) |
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