 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AD9545 Datasheet(PDF) 66 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD9545 Datasheet(HTML) 66 Page - Analog Devices |
|
|
66 / 157 page  AD9545 Data Sheet Rev. A | Page 66 of 157 DC > 50% BALANCED MODULATION UNBALANCED MODULATION MODULATION EVENT DC = 50% 50% FIRST MODULATION CYCLE SECOND MODULATION CYCLE TIME NOMINAL (50%) NOMINAL (50%) 50% +Δt SECOND PULSE UNALTERED +Δt –Δt Figure 58. Alternate Modulation Polarity TIME BASE EDGE Figure 59. Modulation Synchronization Edges TIME SYNC EDGE MODULATION EVENT MODULATION EVENT 0 1 2 3 SYNC EDGE 0 1 2 3 SIGx SNCx MODULATION PERIOD BASE EDGE BASE EDGE Figure 60. Modulation Synchronization MODULATION SYNC The periodic modulation events produced by the modulators are useful as timing markers for synchronization purposes. Both the balanced and unbalanced modulation schemes use two Q divider output cycles to define a modulation event (see Figure 56 and Figure 57). In the case of unbalanced modulation, the second cycle is unaltered but is still part of the modulation event. As such, the first rising edge of the Q divider output following the second modulation cycle marks the base edge for synchronization purposes (see Figure 59). The synchronization information available from the modulators requires the use of a secondary signal path. This path is the reason the modulators have SIGx and SNCx output signals. The SIGx signals are the modulated waveforms that ultimately propagate to the distribution output pins. The SNCx signals are internal only and carry synchronization information attached to the modulation events corresponding with the associated SIGx signal (for example, SNCA associates with SIGA). The SNCx signal is a pulse coincident with the base edge of the corresponding SIGx signal, as shown in Figure 60. As shown in Figure 48, the SNCx signals route to the DPLL via the hitless/zero delay feedback and sync block of the N-shot/ PRBS controller. The SNCx signals provide synchronization to the N-divider of the corresponding DPLL channel. The device automatically selects the appropriate SNCx signal for the Q divider chosen for feedback (when modulation is in effect for that particular Q divider). The SNCx selection is based on the 3-bit Profile x.y tag mode bit field (where x is 0 or 1 and y is 0 to 5) in Bits[D4:D2] of Register 0x1203, Register 0x1223, Register 0x1243, Register 0x1263, Register 0x1283, Register 0x12A3, Register 0x1603, Register 0x1623, Register 0x1643, Register 0x1663, Register 0x1683, and Register 0x16A3. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
