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Data Sheet

AD9545

Rev. A | Page 99 of 157

CAVEATS OF CASCADED DPLL OPERATION

To activate cascaded DPLL operation, the transition to holdover

or freerun must occur by conventional means, as a result of a

reference invalidation, for example, rather than by means of

forced holdover or freerun via the register map.

The recommendation is to avoid using reference synchronization

when employing cascaded DPLL operation (see the Reference

Synchronization section).

When the profile targeted by the DPLLx inactive profile index

bit field becomes inactive, certain aspects of the target profile

configuration still matter (even though the target profile is

inactive), as follows:

•

The translation type (phase buildout or hitless—see the

Translation Modes section). For phase buildout mode, the

APLL associated with the primary DPLL must be in a

calibrated and locked state. For hitless (internal) mode, the

APLL associated with the primary DPLL must be in a

calibrated and locked state and the selected distribution

path must be active (that is, a sync event has occurred (see

the Distribution Output Clock Synchronization section) on

the channel associated with the secondary DPLL).

•

The device uses the information related to the feedback

configuration of the primary DPLL (even though the

primary DPLL is effectively operating open loop, that is,

holdover or freerun).

•

The user cannot specify fractional feedback division for the

primary DPLL (that is, the device ignores the fractional

portion of the feedback divider when operating in the

cascaded DPLL configuration). Furthermore, the user must

properly program the Profile x.y buildout N-divider bit

field of the targeted inactive profile (even if the targeted

inactive profile is a hitless (internal) profile). See the DPLL

Feedback Divider (N-Divider) section for details relating to

the Profile x.y buildout N-divider bit field.

•

The user cannot specify the external zero delay configuration

for cascaded DPLL operation. That is, the enable profile x.y

external zero delay bit must be Logic 0 (where x is the PLL

channel (0 or 1) and y is the profile number (0 to 5)).

•

The device uses the information related to timestamp

tagging according to the primary DPLL. Specifically, the

tagging mode defined for the feedback path of the primary

DPLL determines whether timestamp tags are available on

the reference input path of the secondary DPLL. Thus, the

targeted inactive profile for the primary DPLL must use a

value of 2, 3, or 4 in the Profile x.y tag mode bit field (where x

is 0 or 1 and y is 0 to 5). In addition, the translation profile for

secondary DPLL must use a value of 1, 3, or 4 in the Profile x.y

tag mode bit field (where x is 0 or 1 and y is 0 to 5).

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