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AD9545 Datasheet(PDF) 102 Page - Analog Devices

Part # AD9545
Description  Quad Input, 10-Output, Dual DPLL/IEEE 1588 1 pps Synchronizer and Jitter Cleaner
PDF  157 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9545 Datasheet(HTML) 102 Page - Analog Devices

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AD9545
Data Sheet
Rev. A | Page 102 of 157
In general, the default values of the APLLx dc offset current
value and APLLx manual charge pump current bit fields yield
the best overall performance. For this reason, the recommendation
is to use only the manual charge pump mode (that is, enable
APLLx manual charge pump current = 1).
APLL LOOP FILTER
The phase errors detected by the PFD drive the charge pump.
The charge pump transfers charge to the loop filter in proportion
to the amount of phase error. The loop filter stores the charge,
which creates a dc voltage that steers the VCO frequency in a
manner that nulls out the phase error.
The loop filter is a resistor and capacitor filter with a low-pass
response characteristic that serves three purposes:
•
Storage of charge originating from the charge pump
•
Attenuation of the high frequency components of the
phase error signal
•
Stabilization of the feedback loop
Figure 82 shows the loop filter schematic. Three of the
components (R1, R3, and C2) are programmable, allowing the
user to tailor the response of the loop filter. The two external
capacitors (3.9 nF and 220 nF) are connected to the LFx and
LDOx pins. These two components are necessary for proper
operation of the loop filter and the internal LDO, respectively.
FROM
CHARGE
PUMP
TO
VCO
R1
LFx
LDOx
220nF
C2
R3
30pF
AD9545
3.9nF
Figure 82. APLL Loop Filter
To program R1, use the 3-bit unsigned APLLx loop filter zero
resistor (R1) bit field (where x is 0 or 1) in Bits[D7:D5] of
Register 0x1082 and Register 0x1482. To program R3, use the
2-bit unsigned APLLx loop filter second pole resistor (R3) bit
field (where x is 0 or 1) in Bits[D1:D0] of Register 0x1082 and
Register 0x1482. To program C2, use the 3-bit unsigned APLLx
loop filter pole capacitor (C2) bit field (where x is 0 or 1) in
Bits[D4:D2] of Register 0x1082 and Register 0x1482. Table 49
shows the relationship between the bit field values and the
values of the loop filter components.
Table 49. APLL Loop Filter Component Values
Bit Field Value
R1 (Ω)
C2 (pF)
R3 (Ω)
0
0
8 (default)
200 (default)
1
250
24
250
2
500
40
333
3
750
56
500
4
1000
72
n/a
5
1250
88
n/a
6
1500
104
n/a
7
1750 (default)
120
n/a
In general, the default filter settings yield the best performance.
While it is generally not necessary to alter the response of the
APLL loop filter, the user can contact Analog Devices for
assistance with determining alternative component values for
the APLL loop filter to tailor the response to specific requirements.



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