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AD9545

Data Sheet

Rev. A | Page 82 of 157

DPLL Loop Filter Base Coefficients

The response of characteristic of a digital loop filter is a

function of digital coefficients. In the case of the AD9545, there

are base coefficients that establish a normalized frequency

response characteristic. The user scales the normalized

response to achieve an absolute response (see the DPLL Loop

Filter Bandwidth section).

The AD9545 offers two independent sets of base coefficients, LFx

(where x is 0 or 1), residing in Register 0x0C00 to Register 0x0C17.

The LF0 coefficients are Alpha 0, Beta 0, Gamma 0, and Delta 0.

The LF1 coefficients are Alpha 1, Beta 1, Gamma 1, and Delta 1.

Each coefficient has two components—a significand and an

exponent (for example, the Alpha Significand 0 and Alpha

Exponent 0 bit fields in Register 0x0C00 to Register 0x0C02,

respectively).

Each DPLL has access to LF0 and LF1 per Figure 70. To specify

which response the loop filter of the DPLL uses, program the

Profile x.y loop filter base bit accordingly (where x is the PLL

channel (0 or 1) and y is the profile number (0 to 5)). Logic 0

(default) selects LF0, whereas Logic 1 selects LF1. The Profile x.y

loop filter base bits reside in Bit D7 of Register 0x1203, Register

0x1223, Register 0x1243, Register 0x1263, Register 0x1283,

0x12A3, Register 0x1603, Register 0x1623, Register 0x1643,

The AD9545 provides default values for LF0 and LF1 resulting

in a default response characteristic. The LF0 default values yield

an open-loop response characteristic with 70° phase margin

(nominal). The LF1 default values yield an open-loop response

characteristic with 88.5° phase margin (nominal). Furthermore,

the LF1 default coefficients yield a nearly flat closed-loop

response with <0.1 dB peaking.

Although it is generally not necessary to alter the response of

LF0 or LF1, the user can contact Analog Devices for assistance

with calculating new base coefficients to tailor the DPLL loop

filters to specific requirements.

DPLL Loop Filter Bandwidth

Because the base coefficients establish a normalized frequency

response, the loop filter requires a scale factor to set the

absolute frequency response. The scale factor resides in the

translation profiles as an unsigned 32-bit Profile x.y loop

bandwidth bit field, as shown in Figure 70 (where x is the PLL

channel (0 or 1) and y is the profile number (0 to 5)). The

Profile x.y loop bandwidth bit fields reside in registers starting

with Address 0x1204, Address 0x1224, Address 0x1244,

Address 0x1264, Address 0x1284, Address 0x12A4, Address

0x1604, Address 0x1624, Address 0x1644, Address 0x1664,

Address 0x1684, and Address 0x16A4.

The frequency units associated with the Profile x.y loop bandwidth

bit field depend on the normalization of the LF0 and LF1 base

coefficients (see the DPLL Loop Filter Base Coefficients section).

However, for the default base coefficients, the normalized

frequency units are µHz (10−6 Hz) for both LF0 and LF1.

For example, to set the 0 dB open-loop bandwidth to 50 Hz,

divide 50 Hz by the normalized frequency established by the

selected set of base coefficients (LF0 or LF1), which is 10−6 Hz

for the default LF0 and LF1 values.

Profile x.y Loop Bandwidth = 50 Hz/10−6 Hz

= 50,000,000

= 0x02FAF080 (hexadecimal)

Note that the 32-bit Profile x.y loop bandwidth bit field implies

a maximum DPLL loop bandwidth of nearly 4.3 kHz. However,

the presence of the NCO gain tuning word filter in the loop (see

the NCO Gain Tuning Word Filter Bandwidth section) puts a

constraint on the maximum DPLL loop filter bandwidth. Table 41

relates the maximum DPLL loop filter bandwidth as a function

of the value of the DPLLx NCO gain filter bandwidth bit field

(where x is 0 or 1). The active translation profile of the DPLL

determines whether the LF0 or LF1 column applies for a given

DPLL channel.

Table 41. Maximum DPLL Loop Filter Bandwidth

DPLLx NCO Gain Filter

Bandwidth Bit Field Value

LF0 Maximum

Loop BW (HZ)

LF1 Maximum

Loop BW (HZ)

1850

305

925

152.5

462.5

76.3

231.3

38.1

115.6

19.1

57.81

9.53

28.91

4.77

14.45

2.38

7.227

1.191

3.613

0.596

1.807

0.298

0.9033

0.149

0.4517

0.745

0.2258

0.037

0.1219

0.019

0.0565

0.009

DPLL NCO

The DPLL NCO requires an external clock source. In the case of

the AD9545, the external clock source drives the XOA and XOB

input pins, from which an integrated PLL synthesizer generates

an approximately 2.4 GHz clock signal.

The DPLL normally operates in closed-loop fashion (that is, as

a PLL), which is the normal operating mode, wherein the loop

filter is the frequency tuning word (FTW) source for the NCO.

However, under certain conditions, the DPLL operates in an

open-loop configuration. Figure 71 differentiates between the

two configurations by means of a switch. A loop controller

determines whether the DPLL is in closed-loop operation

(switch closed) or open-loop operation (switch open), while an

FTW processor determines the FTW source for the NCO.

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