AD9545 datasheet(51/157 Pages) AD

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Data Sheet

AD9545

Rev. A | Page 51 of 157

connects to both drivers, one current source is on and the other

is off, allowing a differential output signal.

Differential HCSL Output

To drive a standard HCSL receiver, refer to Figure 32. This

configuration requires programming the driver settings as

follows: enable OUTxy HCSL = 1 (source current), OUTxy

driver current = 3 (15 mA), and OUTxy driver mode = 0

(single-divider differential). In this mode, the driver expects a

50 Ω termination to ground on each driver output pin. The 15

mA drive current yields 750 mV swing across each 50 Ω load.

LVDS Output

To drive an LVDS receiver using ac coupling, refer to Figure 31.

This configuration requires programming the driver settings as

follows: enable OUTxy HCSL = 1 (source current), OUTxy

driver current = 0 (7.5 mA) and OUTxy driver mode = 0

(single-divider differential). In this mode, the driver expects a

50 Ω termination to ground on each driver output pin and dc

blocking capacitors with a 100 Ω differential termination at the

receiver. The expected termination arrangement yields 188 mV

swing across the 100 Ω load but with 188 mV common-mode

across the output pins, and thus, the need for dc-blocking

capacitors to preserve the common-mode bias of 1.2 V of the

receiver.

To drive an LVDS receiver directly with dc coupling, use a

T network, as shown in Figure 34. This configuration requires

programming the driver settings as follows: enable OUTxy

HCSL = 0 (sink current), OUTxy driver current = 0 (7.5 mA),

and OUTxy driver mode = 0 (single-divider differential). This

arrangement yields a 375 mV swing across the output pins with

1.24 V common mode. When using an additional 100 Ω

differential termination (RL) at the receiver, however, ac

coupling is necessary (as shown in Figure 31). The additional

termination also requires increasing the drive current to 15 mA

(OUTxy driver current = 2). This arrangement yields a 375 mV

swing across the output pins with 0.67 V common-mode (thus

the ac coupling requirement to preserve the 1.2 V common-

mode bias of the LVDS receiver).

To drive an LVDS receiver using a Thevenin equivalent

termination, refer to Figure 35, which exhibits the equivalent of

a 50 Ω pull-up to 1.42 V on each output pin. This configuration

requires programming the driver settings as follows: enable

OUTxy HCSL = 0 (sink current), OUTxy driver current = 0

(7.5 mA), and OUTxy driver mode = 0 (single divider

differential). This arrangement yields a 375 mV swing across

the output pins with 1.23 V common mode.

When using an additional 100 Ω differential termination (RL) at

the receiver, however, ac-coupling is necessary (as shown in

Figure 31), as well as increasing the drive current to 15 mA

(OUTxy driver current = 2). This arrangement yields 375 mV

swing across the output pins with 1.05 V common mode (thus

the ac coupling requirement to preserve the 1.2 V common-

mode bias of the LVDS receiver).

To drive an LVDS like receiver that can handle boosted signal

swing, use a Thevenin equivalent termination per Figure 36,

which exhibits the equivalent of a 50 Ω pull-up resistor to

1.60 V on each output pin.

This configuration requires programming the driver settings as

follows: enable OUTxy HCSL = 0 (sink current), OUTxy driver

current = 2 (15 mA), and OUTxy driver mode = 0 (single-

divider differential). This arrangement yields 750 mV swing

across the output pins with 1.23 V common-mode.

CML Output

To configure an output for CML signals, see Figure 33. When

using a 50 Ω pull-up resistor to 1.2 V, this configuration

requires programming the driver settings as follows: enable

OUTxy HCSL = 0 (sink current), OUTxy driver current = 0

(7.5 mA), and OUTxy driver mode = 0 (single-divider

differential). This arrangement yields a 375 mV swing across

the output pins with 1.01 V common mode.

When using a 50 Ω pull-up resistor to 1.5 V or 1.8 V, increase

the drive current to 15 mA (OUTxy driver current = 2). This

arrangement yields a 750 mV swing across the output pins with

1.125 V common mode for a 1.5 V supply and 1.425 V common

mode for a 1.8 V supply.

Dual, Single-Ended In-Phase Outputs

To configure the output to produce the same signal (in phase)

on each pin of an OUTxyP/OUTxyN pin pair, refer to Figure 37.

This configuration requires programming the driver settings as

follows: enable OUTxy HCSL = 1 (source current) and OUTxy

driver mode = 1 (single-divider, single-ended). Select the driver

current to yield an acceptable voltage swing based on the load

resistance, RL. The output is essentially a current source (on or

off per the logic state of the QXY divider) with an external pull-

down resistor. Thus, the output signal swing is between ground

and V = I × RL.

Independent, Single-Ended Outputs

To configure the output to produce independent signals on the

two output pins of an OUTxyP/OUTxyN pin pair, refer to

Figure 39. This configuration requires programming the driver

settings as follows: enable OUTxy HCSL = 1 (source current)

and OUTxy driver mode = 2 (dual-divider, single-ended).

Select the driver current to yield an acceptable voltage swing

based on the load resistance, RL. Note that the output is

essentially a current source (on or off per the logic state of the

Qxy and Qxyy dividers) with an external pull-down resistor.

Thus, the output signal swing is between ground and V = I × RL.

OUTPUT DRIVER RESET

Because driver pairs (OUT0AP and OUT0AN, for example) are

configurable as differential or single-ended, when the Q dividers

associated with a driver pair stop toggling (due to a divider

reset, for example) the output state of the driver pair is unknown.

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