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AD9545

Data Sheet

Rev. A | Page 56 of 157

DISTRIBUTION PHASE OFFSET CONTROL

OUTPUT PHASE OFFSET OVERVIEW

The phase offset controller (see Figure 47) governs the

application of phase offsets to the individual Q dividers. The

controller implements two categories of phase offset:

•

Initial phase offset

•

Subsequent phase offset

An initial phase offset applies after the device is powered up or

reset and the user issues a sync request that is completed (see

the Distribution Output Clock Synchronization section). The

completed sync request results in the establishment of the initial

phase offset. The value of the initial phase offset is per the 33-bit

unsigned Qxy phase bit field associated with each Q divider

(where x is 0 or 1 and y is A, AA, B, BB, C, or CC) in registers

starting with Address 0x1104, Address 0x110D, Address 0x1116,

Address 0x111F, Address 0x1128, Address 0x1131, 0x1504,

Address 0x150D, Address 0x1516, and Address 0x151F. There

are 10 occurrences of this bit field, one for each Q divider.

Subsequent phase offsets apply for all subsequent sync requests

(that is, any sync requests occurring after the initial power-up

or reset sync request). See the Distribution Output Clock

Synchronization section regarding sync requests.

Iinitial and subsequent phase offsets require the enable Qxy

pulse width control bit of the Q divider to be Logic 0.

INITIAL PHASE OFFSET

The initial phase offset of a particular Q divider is dependent on

the value of its corresponding Qxy divider ratio bit field and

enable Qxy half divide bit, which together constitute the

number of rising and falling input clock edges that span one

period of the Q divider output. For details on the Qxy divider

ratio and Enable Qxy half divide bit fields see the Distribution

Dividers (Q Dividers) section.

In terms of the bit field values defining the divide ratio of the Q

divider,

E = (2 × Qxy Divider Ratio) + Enable Qxy Half Divide

= 2 × QN

where:

E is the total number of input edges per output period of the Q

divider.

is the complete divide factor (for example, 101.5) of a

specific Q divider.

Thus, for QN = 101.5, E = 203.

Use the Qxy phase bit field to program the initial phase offset.

The value of the Qxy phase bit field represents phase offset (θ,

in degrees) as a fraction of E.

θ = 360° × (Qxy Phase/E)

This equation implies that the value of the Qxy phase bit field

must be less than E (that is, the range of Qxy phase is 0 to E − 1).

Note that programming an invalid Qxy phase value results in

the phase offset controller taking no action other than setting

one of the DPLLx phase control error bits associated with the

corresponding Q divider (where x is 0 or 1) in Bits[D5:D0] of

Q0B, Q0AA and Q0A, respectively. For Register 0x320E,

Bits[3:0] correspond to Q1BB, Q1B, Q1AA, and Q1A,

respectively.

The user can access the phase control error results via an

appropriately configured Mx status pin (see the Status and

Control Pins section). The Mx pin output signal constitutes a

logical OR of the DPLLx phase control error bits on a per

channel basis. That is, the logical OR of the six DPLL0 phase

control error bits associated with Channel 0 or the logical OR of

the four DPLL1 phase control error bits associated with

Channel 1.

SUBSEQUENT PHASE OFFSETS

Subsequent phase offsets involve writing a new phase offset

value to the appropriate Qxy phase bit field and then setting the

IO_UPDATE bit. The magnitude of the applied phase offset is

the same as described in the Initial Phase Offset section.

Unlike the initial phase offset, the phase controller implements

subsequent phase offsets in stepwise fashion as a sequence of

phase steps, where the Qxy phase bit field denotes the amount

of phase offset present at the termination of the sequence. The

controller executes the phase steps at a rate commensurate with

the Q divider output period. This mechanism makes it possible

to soften the phase transient that results when applying subsequent

phase offsets. The reason is the stepwise implementation of the

phase offset effectively limits phase transients to some maximum

amount per output cycle of the Q divider, which effectively

constitutes a phase rate of change limiter. The limited rate of

change of phase replaces the relatively large instantaneous phase

step of a phase adjustment with a series of small phase steps,

which reduces the spectral content normally associated with

phase adjustment.

When the Q divider is in the process of phase slewing as a part

of the phase offset sequence, it sets the corresponding DPLLx

phase slew active bit (where x is 0 or 1) in Bits[D5:D0] of

Bits[5:0] correspond to Q0CC, Q0C, Q0BB, Q0B, Q0AA, and

Q0A, respectively. For Register 0x320D, Bits[3:0] correspond to

Q1BB, Q1B, Q1AA, and Q1A, respectively.

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