AD9545 datasheet(77/157 Pages) AD

77 / 157 page

Data Sheet

AD9545

Rev. A | Page 77 of 157

monitor forces it to establish new reference statics (see the

Reference Monitor section).

The phase transient threshold detector provides the user with a

status indicator for the occurrence of a phase step detection.

Phase step detection status is via the DPLLx phase step detected

bit (where x is 0 or 1) in Bit D0 of Registers 0x3011 and 0x3016.

Because these are latched IRQ bits, the user must clear them via

Bit D0 of Register 0x200C and Register 0x2011 to obtain

visibility of subsequent threshold violations detected by the

phase step detector (see the Interrupt Request (IRQ) section).

Mitigating Phase Step Limit False Positives

When enabled, the phase transient threshold detector operates

continuously while the associated reference is the active

reference for the DPLL (DPLL0 or DPLL1), assuming the DPLL

is frequency locked. As such, any phase disturbance at the input

to the phase detector (including user induced phase adjustment

via the DPLLx phase offset bit field (see the DPLL Phase Offset

Control section) or the Profile x phase skew bit field (see the

Skew Adjustment section) is subject to violating the threshold

of the phase transient threshold detector. To mitigate false

triggering of the phase transient threshold detector (when

enabled) due to intentional phase adjustments, the user can

employ the phase slew rate limiter (see the Phase Slew Rate

Limit section).

The following formula relates the maximum phase slew rate

(MPSR) assigned to the phase slew rate limiter necessary to

prevent inadvertent triggering of the phase transient threshold

detector due to a user induced phase disturbance:

MPSR ≤ (P × F)/7

(16)

where:

P is the phase transient threshold detector limit (in picoseconds).

F is the frequency (in Hz) at the input of the DPLL phase

detector. The inequality in Equation 16 ignores other

contributors to phase error such as jitter, frequency offset, and

propagation delay variation, for example. Because MPSR in

Equation 16 constitutes an upper bound, it is best to use a lower

value of MPSR to provide margin (a 25% reduction is

reasonable).

In fact, if the user has advance knowledge of the timing of an

external event such as the switching of the reference input clock

source via an external mux, then rather than using the phase

transient step detector a more robust solution is to invalidate

the associated reference manually. To do so, force a reference

fault condition via the appropriate fault REFx bit field (where x

is A, AA, B, or BB) in Bits[D3:D0] of Register 0x2003. Using

this method imposes the least impact on the steady state

operation of the device. The only steady state impact is that the

validation timer of the associated reference must be set to a

duration that is longer (with suitable margin) than the duration

between the assertion of the force fault condition and the

occurrence of the external event.

SKEW ADJUSTMENT

Skew adjustment allows the user to associate a fixed phase offset

with a reference input, which is useful in applications with

redundant GNSS/GPS reference sources, for example. That is, a

user may have two or more GNSS/GPS sources that have

identical frequency but exhibit a fixed time offset due to a

mismatch between antenna cable lengths.

To activate the skew adjustment feature, program the 24-bit

signed Profile x phase skew bit field (where x is 0 to 7) in

registers starting with Address 0x080E, Address 0x082E,

Address 0x084E, Address 0x086E, Address 0x088E, Address

0x08AE, Address 0x08CE, and Address 0x08EE. The default

value is zero, which disables the skew adjustment feature. A

nonzero value enables the skew adjustment feature and denotes

the desired time skew in units of picoseconds per the following

equation:

Time skew = Profile x Phase Skew × 10−12

(17)

For example, determine the value of the Profile x phase skew bit

field necessary for a time skew of –35 ns. Solving Equation 17

for Profile x phase skew yields the following:

Profile x Phase Skew = Time Skew/10−12

= (–35 × 10−9)/10−12

= –35,000

= 0xFF7748 (hexadecimal)

INITIAL PHASE SKEW REFINEMENT STEPS

Whenever the AD9545 performs a reference switchover, it

performs an initial assessment of the time offset between the

old and new reference. The device does not use the phase of the

new reference to determine the phase offset but compares the

time stamps of the feedback TDC with the time stamps from

the TDC of the new reference (see Figure 67). This comparison

allows the device to insert an opposing time offset into the

servo loop of the DPLL, a phase buildout operation (see the

Frequency Translation Loops section).

By definition, this initial phase offset insertion constitutes a

phase buildout and is a requirement for reference switchover

involving a phase buildout translation profile. However, because

the AD9545 supports both hitless and phase buildout

translation profiles, it can leverage its phase buildout capability

to assess the reference phase offset and build out the initial

phase offset of a hitless switchover as well. By applying phase

buildout at the beginning of a hitless switchover, the AD9545

can significantly reduce the time necessary to complete a hitless

switchover acquisition.

Because the feedback path of the DPLL includes the loop filter,

the feedback signal has the benefit of reduced jitter and an

inherent resistance to change (a consequence of the typically

narrow bandwidth of the loop filter). As such, when the

AD9545 switches to a new reference, the phase and frequency

of the old reference tends to persist in the feedback path of the

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