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Data Sheet

AD9545

Rev. A | Page 55 of 157

Q DIVIDER CONSTRAINTS

Changing the divide ratio of any one of the Q dividers invokes a

synchronization process (see the Autoreconfiguration Sync

Trigger section). The act of changing the divide ratio of a single

Q divider causes a disturbance of all the output clock signals of

the associated PLL channel. Therefore, it is not possible to

change the divide ratio of one Q divider without disturbing all

of the output clock signals of the associated PLL channel.

When the system clock is the selected clock source for a Q

divider pair (see the Distribution Output Clock Synchronization

section), an unlock event on the system clock may cause the Q

divider pair to enter an invalid state. Recovery from this state

requires a divider reset. Therefore, after a system clock unlock

event, the user must follow these steps:

Calibrate the system clock (see the System Clock

Calibration section)

Calibrate APLL0 and APLL1 (see the VCO Calibration

section)

Reset any Q dividers (see the Q Divider Reset section)

using the system clock as an input clock source

Synchronize output distribution (see the Distribution

Output Clock Synchronization section)

When using embedded output clock modulation to modulate

the Q divider output (see the Distribution Embedded Output

Clock Modulation section), a minimum Q divider divide ratio

is necessary:

Qxy ≥ 8

where:

x = 0 or 1.

y = A, B, or C.

When employing the N-shot triggering mechanism to trigger a

Q divider (see the N-Shot Triggering section), a minimum

Q divider divide ratio of 8 is necessary.

Qxy ≥ 8

where:

x = 0 or 1.

y = A, B, or C.

HITLESS/ZERO DELAY FEEDBACK

When configured for hitless/zero delay operation, the DPLL of

the affected PLL channel requires a feedback clock signal to its

N-divider from one of the distribution outputs (see the Internal

Zero Delay (Hitless) Mode section in the Frequency Translation

Loops section). This feedback mechanism is via the hitless/zero

delay feedback and sync block of the N-shot/PRBS controller in

Figure 48. The 5-bit internal/external zero delay feedback path

bit field resides in Bits[D4:D0] of Register 0x1202, Register 0x1222,

0x12A2, Register 0x1602, Register 0x1622, Register 0x1642,

selects the desired Q divider for feedback to the DPLL N-

divider.

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