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AD9545

Data Sheet

Rev. A | Page 50 of 157

DISTRIBUTION CLOCK OUTPUT DRIVERS

OVERVIEW

The AD9545 has 10 clock output pins capable of generating up

to 10 output clock signals. The 10 pins comprise two groups of

clocks differentiated by the PLL channel available as the clock

source driving the group. PLL0 can clock the OUT0 group,

while PLL1 can clock the OUT1 group.

The Output 0 (OUT0) group comprises six of the 10 clock

output pins with the six pins consisting of three pin pairs. Each

pin pair represents an output subgroup (A, B, and C) with the

pins designated as

•

OUT0AP and OUT0AN

•

OUT0BP and OUT0BN

•

OUT0CP and OUT0CN

The Output 1 (OUT1) group comprises the remaining four

output pins consisting of two pin pairs. Each pin pair represents

an output subgroup (A and B) with the pins designated as

•

OUT1AP and OUT1AN

•

OUT1BP and OUT1BN

OUTPUT CURRENT CONTROL

Each pin associated with a subgroup pin pair (OUTxyP/OUTxyN,

where x is 0 or 1 and y is A, B, or C) has a current source and a

channel divider associated with it. The user has the option to set

both subgroup outputs as either source current or sink current

via the enable OUTxy HCSL bit (where x is 0 or 1 and y is A, B

or C) in Bit D0 of Register 0x10D7 to Register 0x10D9 and

current sink mode, while Logic 1 selects current source (or

HCSL) mode.

To control the magnitude of the current, use the OUTxy driver

current bit pairs (where x is 0 or 1 and y is A, B or C) in

Bits[D2:D1] of Register 0x10D7 to Register 0x10D9 and

field value to the magnitude of the driver current.

Table 31. Output Driver Current

OUTxy Driver Current Bit Field Value

Output Current (mA)

7.5 (default)

12.5

Not applicable

OUTPUT MODE CONTROL

The user has control over how each subgroup pin pair relates to

the channel dividers of the subgroup via the OUTxy driver

mode bit field (where x is 0 or 1 and y is A, B, or C) in

Bits[D4:D3] of Register 0x10D7 to Register 0x10D9 and

The single divider modes use only the Qxy divider (with the

Qxyy divider powered down). The dual divider mode makes

use of both the Qxy and Qxyy dividers.

In single-divider differential mode, the clock signal at the

OUTxyN pin phase is inverted relative to the OUTxyP pin.

Figure 32 shows an example of single-divider differential mode.

In single-divider single-ended mode, the clock signals at the

OUTxyP and OUTxyN pins are in phase relative to one another.

Figure 37 shows an example of single-divider single-ended mode.

In dual-divider single-ended mode, the Qxy divider drives the

OUTxyP pin and the Qxyy divider drives the OUTxyN pin. In

this mode, each output of the subgroup can have a different

frequency and phase offset. Figure 39 shows an example of

dual-divider single-ended mode.

Table 32. Driver Output Mode

OUTxy Driver Mode Bit Field

Value

Output Driver Mode

Single-divider differential

(default)

Single-divider single-ended

Dual-divider single-ended

Not applicable

OUTPUT DRIVER CONFIGURATIONS

Table 33 shows a summary of the pertinent driver control bit

field names and corresponding registers (where x is 0 or 1

and y is A, B, or C). The various driver control settings have

corresponding driver termination requirements.

Table 33. Output Driver Control Summary

Bit Field Name

Registers

Enable OUTxy HCSL

Regsiter 0x10D9, Bit 0

OUTxy Driver Current

OUTxy Driver Mode

Each pin of an output pin pair (OUTxyP/OUTxyN) has an

independent driver capable of either sourcing or sinking

current (via the enable OUTxy HCSL bit). Note, however, that

the source/sink selection applies to both current sources of an

output pin pair (that is, either both pin drivers source current or

both pin drivers sink current per the enable OUTxy HCSL bit).

The current source (or sink) of the individual driver is either on

or off, depending on the logic level it receives from the Qxy or

Qxyy divider (0 = off, 1 = on). the Qxy divider has normal and

inverted logic outputs, which means when the Qxy divider

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