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Data Sheet

AD9545

Rev. A | Page 93 of 157

bit field has fresh data. However, the DPLLx history updated bit

is a latched bit; therefore, it indicates that the DPLLx tuning

word history bit field has data, but not necessarily the most

recent data.

DPLLx Clear History Bit

The user can clear the averaging history at any time via the

DPLLx clear history bit (where x is 0 or 1) in Bit D1 of

Logic 1 forces the averaging processor to clear the averaging

circuitry, thereby erasing any previous tuning word history

information and forces the DPLLx history available bit to

Logic 0 (until a newly computed initial average is available).

Programming the DPLLx history available bit to Logic 1 does

not clear the contents of the DPLLx tuning word history bit

field. That is, the last update of this register remains intact until

the processor calculates a new average and sets the DPLLx history

updated bit, thereby notifying the user a new average is available.

DPLLx Single Sample History Bit

When the DPLL must make a switch from active closed-loop

operation to holdover operation, it attempts to use the tuning

word history from the averaging processor. However, if the

averaging processor has not yet set the DPLLx history available

bit (indicating no history is available), then the DPLL, by

default, uses the DPLLx freerun tuning word bit field as the

tuning word for the NCO. Alternatively, the user can have the

DPLL use the most recent tuning word from the loop filter

instead. To use this feature, write a Logic 1 to the DPLLx single

sample history bit (where x is 0 or 1) in Bit D1 of Register

0x100E and Register 0x140E.

DPLLx Quick Start History Bit

Normally, when the DPLL is in active closed-loop operation,

the averaging processor must process tuning words for at least

the amount of time prescribed by the DPLLx history accumulation

timer bit field to compute a full tuning word history average

and to set the DPLLx history available bit (thereby indicating

the averaging processor has processed enough tuning words to

compute an initial average). However, the user has the option of

allowing the averaging processor to indicate the history is

available earlier, by writing a Logic 1 to the DPLLx quick start

history bit (where x is 0 or 1) in Bit D2 of Register 0x100E and

sets the DPLLx history available bit after the first two

subintervals expire and updates the DPLLx tuning word history

bit field. Updates of the DPLLx tuning word history bit field

continue every subinterval thereafter.

During the first eight subintervals of the quick-start history

sequence, the second and third subintervals exhibit a two

subinterval averaging window. The fourth, fifth, sixth, and

seventh subintervals exhibit a four subinterval averaging

window. Finally, the eighth subinterval exhibits an eight

subinterval averaging window, which remains the case for all

subsequent subintervals.

The quick start feature is useful when the time span dictated by

the DPLLx history accumulation timer bit field is very large

(hours, for example). The quick start feature allows the

averaging processor to make an initial tuning word average

available after ¼ of the time indicated by the DPLLx history

accumulation timer bit field.

The DPLLx single sample history bit and the DPLLx quick start

history bit are not mutually exclusive. Both can be set,

providing both options simultaneously with the state of the

averaging processor dictating which option is applicable for the

prevailing conditions. Following a switch from active closed-

loop operation to holdover operation, the progress made by the

averaging processor in computing the initial tuning word

average directs the action of the tuning word processor

according to the state of the DPLLx single sample history bit

and the DPLLx quick start history bit.

DPLLx Persistent History Bit

The DPLLx persistent history bit (where x is 0 or 1) works in

conjunction with the control bits described in the Averaging

Processor Continue or Reset section. The DPLLx persistent

history bit resides in Bit D0 of Register 0x100E and

When DPLLx persistent history is Logic 0, the tuning word

processor resets the averaging processor based on the control

bits described in the Averaging Processor Continue or Reset

section below. When DPLLx persistent history is Logic 1, it

prevents the tuning word processor from clearing the averaging

processor based on the control bits described in the Averaging

Processor Continue or Reset section. Instead, the averaging

processor holds onto its previous computation. That is, the

computation pauses or persists.

Averaging Processor Continue or Reset

By default, the averaging processor continues to compute a

rolling average regardless of the state of the DPLL. The

following three bits (where x is 0 or 1 as appropriate) provide

optional control over resetting or pausing the averaging

processor based on the DPLL state:

•

DPLLx pause history phase unlock

•

DPLLx pause history frequency unlock

•

DPLLx pause history while phase slew limiting

These bits pause or reset the averaging process depending on

the DPLLx persistent history bit. When DPLLx persistent

history = 0, these three bits cause the averaging processor to

reset. When DPLLx persistent history = 1, these three bits cause

the averaging processor to pause (and then resume when the

conditions dictate).

The DPLLx pause history phase unlocked bit in Bit D0 of

averaging processor when the DPLL is not phase locked.

The DPLLx pause history frequency unlock bit in Bit D1

of Register 0x100F and Register 0x140F pauses or resets the

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