AD9545 datasheet(45/157 Pages) AD

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Data Sheet

AD9545

Rev. A | Page 45 of 157

As such, the reference monitor remains in a reset state until the

system clock status is locked and stable, at which time the

reference monitor state machine activates.

The AD9545 has the ability to perform system clock

compensation (see the System Clock Compensation section).

The user has the option to enable the reference monitor to use

the compensated system clock for estimating the reference

period (assumes programming of the appropriate system clock

compensation controls).

REFERENCE PERIOD JITTER ESTIMATION

The main purpose of the reference monitor is to verify the

reference period satisfies the requirements per the tREF, ΔTOL,

ΔHYS, and JTOL parameters provided by user input via the

free, the reference monitor can verify the reference period by

simply measuring the time between successive rising edges.

However, real-world signals are inherently noisy and possess

timing jitter.

Jitter introduces uncertainty in the time measurement between

successive rising edges of the reference signal. Not only is this

true for the reference signal, but also for the internal time base

the monitor uses to make its measurements. Both jitter sources

compromise the ability of the monitor to determine when the

reference is truly in or out of tolerance. That is, jitter dilutes the

confidence of the monitor in making an accurate decision. The

device has no inherent knowledge of the magnitude or spectral

distribution of the jitter present on a particular reference.

Furthermore, the jitter characteristics can vary over time.

Because the monitor uses numeric time stamps to measure the

reference period, it can estimate the variance of the reference

signal as it observes period samples. The variance estimate gives

the monitor some idea of the actual jitter present on the

reference signal. By comparing the variance estimate with the

ΔTOL value provided by the user, the monitor determines how

many period samples are needed to arrive at a period estimate

with sufficient confidence to make an in or out of tolerance

decision. This algorithm enables the monitor to perform a high

confidence period estimate using a nearly optimal minimum

observation time.

Another benefit of this statistical approach to monitoring the

reference period is the monitor does not need to measure the actual

period of the reference. It only needs to estimate the deviation of

the period relative to the scaled TREF value to a sufficiently high

degree of confidence. The reference monitor algorithm has the

necessary confidence requirement built into its design.

Because the reference monitor is able to assess the amount of

reference jitter present via its variance estimate, it has the ability

to determine if there is excessive jitter on the input signal and

indicate such via the JEXCESS status indicator. JEXCESS status is via

the REFx excess jitter bit (where x is A, AA, B, or BB) in Bit D2

of Register 0x3005 to Register 0x3008. Excessive jitter is jitter

greater than the predefined threshold limit as defined by the

input of the user determined JTOL value (see the Reference

Monitor Controls section).

REFERENCE MONITOR DECISION TIME

The reference period estimation algorithm takes into account

the value of ΔTOL specified by the user (see the Reference

Monitor Controls section) and the actual jitter present on the

reference signal. In general, it is the ratio of the square root of

the measured jitter variance to ΔTOL that governs the decision

time of a marginally out of tolerance reference signal. The

smaller the variance of the measured jitter, the less averaging

that is necessary and the shorter the decision making time. The

key point is that it is both the value of ΔTOL and the actual

jitter present that governs the decision time for declaring an out

of tolerance condition. That is, the decision time is not

deterministic.

Although jitter plays a role in the decision time of the reference

monitor under normal operation, it has little effect on the

decision time when the reference period is much greater than

the scaled tREF value (that is, tREF divided by the R-divider factor)

or when the reference signal disappears completely. The

reference monitor relies on time stamps generated by reference

signal edges to perform a reference period estimation. Thus, a

catastrophic loss of the reference signal is problematic, as the

reference signal edges cease to exist, thereby stalling the period

estimation process of the reference monitor.

However, because the reference monitor knows the scaled tREF

value, it can rely on its local time base to watch for the next

expected TDC input edge (note the reference monitor allows

15% excess margin for its expectation of the next reference

input edge). If the reference monitor fails to observe the next

reference input edge within a period of 115% of the scaled tREF

value, then the monitor declares a loss of signal (LOS), see

Figure 43. LOS status is via the REFx LOS bit (where x is A, AA,

B, or BB) in Bit D5 of Register 0x3005 to Register 0x3008.

After the first assertion of the LOS status bit, the LOS bit toggles

on each subsequent occurrence of the expected period of the

reference. Therefore, the LOS bit is not a reliable indicator of

the loss of the reference signal. Instead, the user relies on the

OOT signal as an indicator of the loss of the signal.

REFERENCE VALIDATION

When a reference is in a faulted state (OOT = 1, see Figure 43),

the reference monitor continues to monitor the reference signal

for an in tolerance condition. When the reference returns to in

tolerance, OOT = 0, indicates a nonfaulted condition. OOT

status is via the REFx fault bit (where x is A, AA, B, or BB) in

Bit D3 of Register 0x3005 to Register 0x3008.

Some applications require a reference to be in a nonfaulted

condition for a prescribed period before the reference can be

considered valid. To accommodate these applications, the

reference monitor includes a programmable validation timer.

When a reference transitions from a faulted state to a nonfaulted

state, it indicates a start event for the validation timer, which

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