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Data Sheet

AD9545

Rev. A | Page 79 of 157

DIGITAL PLL (DPLL)

DPLL OVERVIEW

Note that throughout this section, unless otherwise specified,

any referenced bits, registers, or bit fields reside in the DPLL

Channel 0 and DPLL Channel 1 registers (Address 0x1000 to

Address 0x102A, and Address 0x1400 to Address 0x142A) of

the register map.

The DPLL is an all digital implementation of a phase-locked

loop (PLL). Figure 68 shows the fundamental building blocks of

an APLL and a DPLL. An APLL typically relies on a VCO as the

frequency element for generating an output signal, where the

output frequency depends on an applied dc voltage. A DPLL,

conversely, uses a numerically controlled oscillator (NCO),

which relies on a digital frequency tuning word (FTW) to

produce the output frequency. A VCO inherently produces a

timing signal because it is, by definition, an oscillator, whereas

the AD9545 NCO requires an external timing source, the system

clock. The fundamental difference between an APLL and a

DPLL is that the VCO in an APLL can tune to any frequency

within its operating bandwidth, whereas the NCO in a DPLL

can only tune to discrete frequencies (by virtue of the FTW).

PHASE

DETECTOR

DIVIDER

LOOP

FILTER

VCO

ANALOG

PHASE

ERROR

VOLTAGE

FIXED LOOP

BANDWIDTH

APLL

DIGITAL

PHASE

DETECTOR

DIVIDER

DIGITAL

LOOP

FILTER

NUMERIC

PHASE

ERROR

SYSTEM

CLOCK

PROGRAMMABLE

LOOP BANDWIDTH

DPLL

NCO

NUMERIC

COEFFICIENTS

NUMERIC

FREQUENCY

TUNING WORD

Figure 68. APLL vs. DPLL

The DPLLs in the AD9545 have a digital TDC-based phase

detector and a digital loop filter with programmable bandwidth.

The digital loop filter output yields a digital FTW (instead of a

dc voltage, as in the case of an analog PLL) that produces a

corresponding NCO output frequency.

DPLL LOOP CONTROLLER

The DPLL has several operating modes (including freerun,

holdover, and active). To ensure seamless transition between

modes, the DPLL has a loop controller. The loop controller sets

the appropriate DPLL operating mode based on the prevailing

requirements of automatic reference switching or manual

control settings.

Switchover

Switchover occurs when the loop controller switches directly

from one input reference to another (see the Reference

Switching section). The AD9545 handles a reference switchover

by briefly entering holdover mode, loading the new DPLL

parameters, and then immediately recovering.

Holdover or Freerun

Typically, the holdover or freerun state is in effect when all of

the input references are invalid. However, the user can force the

holdover mode even when one or more references are valid by

setting the DPLLx force holdover bit (where x is 0 or 1) to Logic 1

(Bit D1 of Register 0x2105 and Register 0x2205). To force freerun

mode, see the Freerun Tuning Word section. In holdover mode,

the output frequency remains fixed (to the extent of the stability

of the system clock). The accuracy of the AD9545 in holdover

mode is dependent on the device programming and availability

of the tuning word history.

When the DPLL is in holdover or freerun mode, it implies there

is no active translation profile available (see the Frequency

Translation Loops section). However, the DPLL is still attached

to a translation profile by virtue of the DPLLx inactive profile

index bit field (where x is 0 or 1) in Bits[D2:D0] of Register 0x102A

or Register 0x142A. The DPLLx inactive profile index bit field

defines which translation profile attaches to the DPLL when in

holdover or freerun mode.

Because the DPLL attaches to the profile specified by the

DPLLx inactive profile index bit field, the recommendation is

for the user to program the DPLLx inactive profile index bit

field with one of the translation profiles the user has purposefully

configured. For example, if the user configures Translation

Profile 0, Translation Profile 2, and Translation Profile 5 for use

by DPLL0, program the DPLL0 inactive profile index bit field

with 0, 2, or 5.

Recovery from Holdover

When in holdover and an enabled translation profile becomes

available, the device exits holdover operation. The loop controller

restores the DPLL to closed-loop operation, locks to the selected

reference, and sequences the recovery of all the loop parameters

based on the profile settings for the active reference.

If DPLLx force holdover = 1, the device does not automatically

exit holdover when a valid translation profile is available.

However, automatic recovery of a valid translation profile can

occur after clearing the DPLLx force holdover bit.

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