AD9545 datasheet(101/157 Pages) AD

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Data Sheet

AD9545

Rev. A | Page 101 of 157

APLL FEEDBACK DIVIDER (M-DIVIDER)

The user programs the APLL feedback M-divider via the 8-bit

unsigned APLLx Mx feedback divider bit fields (where x is 0 or

1) in Register 0x1081 and Register 0x1481. The divide ratio of

the M-divider is the value, M, the user programs in the APLLx

Mx feedback divider bit fields. The M-divider provides divide

ratios from 1 to 255. The M-divider interprets a value of 0 as 1.

For a desired divide ratio of 27, the required bit field value is 27

(0x1B hexadecimal).

PHASE/FREQUENCY DETECTOR (PFD)

The PFD detects the instantaneous phase error between the

feedback signal from the M-divider and the output from the

DPLL. The phase error essentially drives the servo loop of the

APLL in a manner that ultimately nulls out the phase difference

between the two signals. The PFD bandwidth is wide enough to

handle signals originating from the NCO of the DPLL (up to

~350 MHz nominal).

The APLLs incorporate lock detection circuitry that indicates

when they achieve a frequency locked condition. Locked status

indication is available via the APLLx lock bit in Bit D3 of

locked status. These bits are also available as an output signal

via an appropriately configured Mx pin.

The IRQ section of the register map provides the APLLx locked

and APLLx unlocked bits (where x is 0 or 1) in Bits[D3:D2] of

status indicated by the name of the bit. Because these bits are

part of the IRQ mechanism (see the Interrupt Request (IRQ)

section), they constitute latched indicators of the status of the

APLL lock detector. The user must clear the APLLx locked and

APLL unlocked bits via Bits[D3:D2] of Register 0x200F and

APLL lock or unlock state.

CHARGE PUMP

The charge pump consists of a pair of constant current sources

that deliver charge to or remove charge from the loop filter

based on the output of the phase detector. The transfer of

charge increases or decreases the voltage applied to the VCO,

which steers the VCO frequency to match the input frequency

and ultimately bring about a phase locked condition.

The charge pump has two operating modes, manual and

automatic, selectable via the enable APLLx manual charge pump

current bit (where x is 0 or 1) in Bit D7 of Register 0x1080 and

whereas Logic 0 selects automatic mode.

In manual mode, the user programs the charge pump current

via the 7-bit unsigned APLLx manual charge pump current bit

field (where x is 0 or 1) in Bits[D6:D0] of Register 0x1080 and

field value as follows:

ICP

= APLLx Manual Charge Pump Current × 8 µA

(22)

ICP allows a current range of 0 µA to 1016 µA. The default bit

field value yields 128 µA.

For example, given ICP = 743 µA, determine the value of the APLLx

manual charge pump current bit field. Solving Equation 22 for

the bit field value yields

APLLx Manual Charge Pump Current = ICP

/8 µA

= 743 µA/8 µA

= 93 (nearest integer)

= 0x5D (hexadecimal)

In automatic mode, the APLLx manual charge pump current bit

field is ineffective. Instead, the APLL automatically adjusts the

charge pump current (ICP) based on the value of the M-divider

according to Table 47. This automatic adjustment yields a

relatively constant loop bandwidth for M-divider values from

1 to 63. The loop bandwidth is ~250 kHz for APLL0 and ~300 kHz

for APLL1. Note that automatic charge pump control is only valid

over a subset of M-divider values. In light of this constraint, it is

generally best practice to avoid automatic mode.

Table 47. APLL Charge Pump Current in Automatic Mode

M-Divider Value

ICP

1 to 63

M × 16 µA

64 to 255

1016 µA

Regardless of the operating mode (manual or automatic), the

charge pump has a provision for applying a constant dc offset

current to the output of the charge pump. Injection of an offset

current overcomes some of the spectral artifacts associated with

charge pump nonlinearity when the APLL is in a locked state.

Generally, noise performance improves significantly when this

feature is active and properly adjusted.

To enable/disable the dc offset current feature use the enable

APLLx dc offset current bit (where x is 0 or 1) in Bit D0 of

this feature, whereas Logic 0 disables it. To control the polarity

(positive or negative) of the offset current, use the APLLx dc offset

current direction bit (where x is 0 or 1) in Bit D3 of Register 0x1083

and Register 0x1483. Logic 0 (default) is positive, whereas Logic 1 is

negative. The magnitude of the offset current depends on the value

of the 2-bit unsigned APLLx dc offset current value bit field (where

x is 0 or 1) in Bits[D2:D1] of Register 0x1083 and Register 0x1483.

The value of this bit field sets the dc offset current as a fraction of

ICP per Table 48, but with a granularity of 8 µA. Thus, the offset

current is in integer steps of 8 µA, with fractions of an 8 µA step

rounded in the direction of zero (that is, −53 µA rounds to

−4 µA).

Table 48. APLL Charge Pump DC Offset Current

APLLx DC Offset Current

Value Bit Field Value

DC Offset Current (% of ICP)

25 (default)

12.5

6.25

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