Low Battery Detect (LBD) - Low Voltage Reset
112
PRELIMINARY V1.8
TABLE 77.
Definition of LBDCR
Read/Write
by Software
R/W
R/W
R/
W
R/
W
R/W
R/W
R/W
R/W
Write
by Hardware
Name
Bit
Description
TST
7
Test Mode Enable
[Bit Status: 0 (Initial Value)]
This status corresponds to normal operation.
[Bit Status: 1]
This status corresponds to test mode. In the test mode the comparator
output is written to bit 6 of this control register while the interrupt and
reset outputs of the LBD are disabled.
CMP_OUT
6
Test Mode Comparator Output
When in test mode, bit 7 set, this register will reflect the output
of the comparator.
5 to 3
Reserved bit
AN_ENB
3
Analog input enable
[Bit Status: 0 (Initial Value)]
This status is to set the i/o for the SS1102C. The default is to make it
analog input and disable the digital input to the port.
[Bit Status: 1]
This status is to enable the digital input for the i/o port.
LVS[1:0]
2 to 1
Voltage Level select bits
[Bit Status: 00 (Initial Value)]
This status corresponds to a low battery detect voltage of 2.9V, level 4.
[Bit Status: 01]
This status corresponds to a low battery detect voltage of 2.8V, level 3.
[Bit Status: 10]
This status corresponds to a low battery detect voltage of 2.7V, level 2.
[Bit Status: 11]
This status corresponds to the low voltage reset detect of 2.6V, level 1
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