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IP175DLF Datasheet(PDF) 108 Page - List of Unclassifed Manufacturers

Part # IP175DLF
Description  5 Port 10/100 Ethernet Integrated Switch (Loop Detection, Layer 2-4 MF Classifier, HW IGMP Snooping)
PDF  145 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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IP175DLF Datasheet(HTML) 108 Page - List of Unclassifed Manufacturers

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IP175DLF
Datasheet
108/145
August 22, 2014
Copyright © 2007, IC Plus Corp.
IP175DLF-DS-R10.1
5.9
Miscellaneous Control Register
PHY
MII
ROM
R/W
Description
Default
22[15]
RESERVED
REDUCE_IPG
This function reduce the IPG by random from 0~20 PPM
1: enable
0: disable
Default Value
Pin 113 MII2_EN=1
Pin 113 MII2_EN=0
22[14]
51[6]
R/W
0
Pin 97(1)
*
22[13]
51[5]
R/W TWOPARTD
Reset the inter-frame-gap counter to zero, if the CRS signal
asserted during the two third of IPG period.
1: enable
0 disable
1’b1
22[12]
51[4]
R/W HP_DIS_FLOW_EN
High priority packet to disable flow control
1: a port will disable its flow control function for 2 sec if it
receives a high priority packet.
0: the function is disabled
1’b0
22[11:10] 51[3:2]
R/W DRIVE[1:0]
Pad driving capability selection
00: 4 mA
01: 8 mA
10: 12 mA
11: 16 mA
2’b01
22[9:8]
RESERVED
22[3]
50[5]
R/W LINK_Q_EN,LINK quality enable
1:enable (default)
0:disable
pin_101
(1)
22[2]
50[4]
R/W TB31_EN
Turbo MII0 31.25MHZ output enable
1: Turbo MII mode (MII0) output 31.25MHZ MIICLK
0: Turbo MII mode (MII0) output 50MHZ MIICLK
1’b0
22[1]
50[3]
R/W STAG_TX_EN
Special tagging for TX enable
1: enable
0: disable
1’b0
21
22[0]
50[2]
R/W STAG_RX_EN
Special tagging for RX enable
1: enable
0: disable
1’b0



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