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IP175DLF Datasheet(PDF) 106 Page - List of Unclassifed Manufacturers

Part # IP175DLF
Description  5 Port 10/100 Ethernet Integrated Switch (Loop Detection, Layer 2-4 MF Classifier, HW IGMP Snooping)
PDF  145 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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IP175DLF Datasheet(HTML) 106 Page - List of Unclassifed Manufacturers

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IP175DLF
Datasheet
106/145
August 22, 2014
Copyright © 2007, IC Plus Corp.
IP175DLF-DS-R10.1
PHY
MII
ROM
R/W
Description
Default
18[15:14]
--
R/W
FILTER_INFO
2’b00
18[13:10]
--
R/W
PRI_INFO
4’h0
18[9:6]
--
R/W
FID
4’h0
18[5:0]
--
R/W
PORT_MAP
Note –If PORT_MAP set to all zero, frame’s DMAC matched
this entry is discarded.
6’h0
19[15:2]
RESERVED
19[1]
--
R/W
VALID
Entry is valid.
1’b0
19[0]
--
R/W
IGMP
This bit shall set to 0.
1’b0
5.7.4
Data Buffer Register (For IP Multicast Address)
PHY
MII
ROM
R/W
Description
Default
15[15:0]
--
R/W
MAC_ADDR[15:0]
16’h0000
16[15:14]
--
R/W
TIMEOUT_P2[1:0]
2’b00
16[13:11]
--
R/W
TIMEOUT_P1[2:0]
3’b000
16[10:8]
--
R/W
TIMEOUT_P0[2:0]
3’b000
16[7]
--
R/W
MAC_ADDR[23]
This bit shall be set to 0.
1’b0
16[6:0]
--
R/W
MAC_ADDR[22:16]
7’h0
17[15:10]
RESERVED
17[9:7]
--
R/W
TIMEOUT_P5[2:0]
3’b000
17[6:4]
--
R/W
TIMEOUT_P4[2:0]
3’b000
17[3:1]
--
R/W
TIMEOUT_P3[2:0]
3’b000
17[0]
--
R/W
TIMEOUT_P2[2]
1’b0
18[15:14]
--
R/W
FILTER_INFO
2’b00
18[13:10]
--
R/W
PRI_INFO
4’h0
18[9:6]
--
R/W
FID
4’h0
18[5:0]
--
R/W
PORT_MAP
Note – If PORT_MAP set to all zero, frame’s DMAC matched
this entry is discarded.
6’h0
19[15:2]
RESERVED
19[1]
--
R/W
VALID
Entry is valid.
1’b0
21
19[0]
--
R/W
IGMP
This bit shall set to 1.
1’b1



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