TMS320F datasheet(126/389 Pages) TI

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ADDC

Add to Accumulator With Carry

7-26

Syntax

ADDC

dma

Direct addressing

ADDC

ind [, ARn]

Indirect addressing

Operands

dma:

7 LSBs of the data-memory address

Value from 0 to 7 designating the next auxiliary register

ind:

Select one of the following seven options:

*–

*0+

*0–

*BR0+

*BR0–

ADDC

dma

987

6543

210

dma

ADDC

ind [, ARn]

987

6543

210

ARU

NAR

Note:

ARU, N, and NAR are defined in section 6.3,

Indirect Addressing Mode (page 6-9).

Execution

Increment PC, then ...

(ACC) + (data-memory address) + (C)

→ ACC

Status Bits

Affected by

Affects

OVM

C and OV

This instruction is not affected by SXM.

Description

The contents of the addressed data-memory location and the value of the

carry bit are added to the accumulator with sign extension suppressed. The

carry bit is then affected in the normal manner: the carry bit is set (C = 1) if the

result of the addition generates a carry and is cleared (C = 0) if it does not gen-

erate a carry.

The ADDC instruction can be used in performing multiple-precision arithmetic.

Words

Cycles for a Single ADDC Instruction

Program

Operand

ROM

DARAM

SARAM

External

DARAM

1+p

SARAM

1, 2†

1+p

External

1+d

2+d+p

† If the operand and the code are in the same SARAM block

Opcode

Cycles

TMS320F Datasheet(PDF) 126 Page - Texas Instruments

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