TMS320F datasheet(130/389 Pages) TI

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ADDT

Add to Accumulator With Shift Specified by TREG

7-30

Syntax

ADDT

dma

Direct addressing

ADDT

ind [, ARn]

Indirect addressing

Operands

dma:

7 LSBs of the data-memory address

Value from 0 to 7 designating the next auxiliary register

ind:

Select one of the following seven options:

*–

*0+

*0–

*BR0+

*BR0–

ADDT

dma

987

6543

210

dma

ADDT

ind [, ARn]

987

6543

210

ARU

NAR

Note:

ARU, N, and NAR are defined in section 6.3,

Indirect Addressing Mode (page 6-9).

Execution

Increment PC, then ...

(ACC) + [(data-memory address)

2(TREG(3:0))] → (ACC)

Status Bits

Affected by

Affects

SXM and OVM

C and OV

Description

The data-memory value is left shifted and added to the accumulator, and the

result replaces the accumulator contents. The left shift is defined by the four

LSBs of the TREG, resulting in shift options from 0 to 15 bits. Sign extension

on the data-memory value is controlled by SXM. The carry bit (C) is set when

a carry is generated out of the MSB of the accumulator; if no carry is generated,

the carry bit is cleared.

Words

Cycles for a Single ADDT Instruction

Program

Operand

ROM

DARAM

SARAM

External

DARAM

1+p

SARAM

1, 2†

1+p

External

1+d

2+d+p

† If the operand and the code are in the same SARAM block.

Opcode

Cycles

TMS320F Datasheet(PDF) 130 Page - Texas Instruments

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