VT8235 datasheet(140/145 Pages) VIA

140 / 145 page

VT8235 V-Link South Bridge

Revision 1.22 October 24, 2002

-134-

Functional Descriptions

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Power Management Events

Three types of power management events are supported:

1) ACPI-required Fixed Events defined in the PM1a Status

and PM1a Enable registers.

These events can trigger

either SCI or SMI depending on the SCI Enable bit:

• PWRBTN# Triggering

• RTC Alarm

• Sleep Button

• ACPI Power Management Timer Carry (always SCI)

• BIOS Release (always SCI)

2) ACPI-aware General Purpose Function Events defined

in the GP Status and GP SCI Enable, and GP SMI Enable

registers.

These events can trigger either SCI or SMI

depending on the setting of individual SMI and SCI

enable bits:

• External SMI triggering

• USB Resume

• Ring Indicator (RI#)

• Battery Low Detect (BATLOW#)

• Notebook Lid Open/Close Detect (LID)

• Thermal Detect (THRM#)

3) Generic Global Events defined in the Global Status and

Global Enable registers. These registers are mainly used

for SMI:

• PCI Bus Clock Run Resume

• Primary Interrupt Occurance

• GP0 and GP1 Timer Time Out

• Secondary Event Timer Time Out

• Occurrence of Primary Events

(defined in the Primary Activity Status and Primary

Activity Enable registers)

• Legacy USB accesses (keyboard and mouse)

- Software SMI

System and Processor Resume Events

Depending on the system suspend state, different features can

be enabled to resume the system. There are two classes of

resume events:

VSUS-based events.

Event logic resides in the

VSUS plane and thus can resume the system from

any suspend state. Such events include PWRBTN#,

RI#, BATLOW#, LID, SMBus resume event, RTC

alarm, EXTSMI#, and GP1 (EXTSMI1#).

VCC-Based Events. Event logic resides in the VCC

plane and thus can only resume the system from the

POS state. Such events include the ACPI PM timer,

USB resume, and EXTSMIn#.

Figure 4. System Block Diagram Using the VT8754 North Bridge

HCLK

GCLK

Host CPU

CPU

Bus

CKE#

Memory Bus

SMBus

LPC

VT8754

North

Bridge

(P4X333

Chipset)

DDR

SDRAM

Graphics

Controller

AGP Bus

PCISTP#

GPIO and ACPI Events

BIOS ROM

GCKRUN#

PCI Bus

IDE

USB 2

Power Plane & Peripheral Control

VT8235

South

Bridge

Keyboard / Mouse

CPUSTP#

Clock

Generator

MCLK

HCLK

GCLK

PCLK

SMI# / STPCLK#

SUSCLK,

SUSST1#

SMIACT#

Module ID

PHY

MII

10 / 100BaseT Lan

AC97

V-Link

Interface

PCKRUN#

PCLK

VT8235 Datasheet(PDF) 140 Page - VIA Technologies, Inc.

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