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PM7346 Datasheet(PDF) 285 Page - PMC-Sierra, Inc |
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PM7346 Datasheet(HTML) 285 Page - PMC-Sierra, Inc |
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285 / 419 page ![]() PM7346 S/UNI-QJET DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3 PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE 264 Register 098H, 198H, 298H, 398H: RBOC Configuration/Interrupt Enable Bit Type Function Default Bit 7 Unused X Bit 6 Unused X Bit 5 Unused X Bit 4 Unused X Bit 3 Unused X Bit 2 R/W IDLE 0 Bit 1 R/W AVC 0 Bit 0 R/W FEACE 0 FEACE: The FEACE bit enables the generation of an interrupt when a valid far end alarm and control (FEAC) code is detected. When a logic 1 is written to FEACE, the interrupt generation is enabled. AVC: The AVC bit position selects the validation criterion used in determining a valid FEAC code. When a logic 0 is written to AVC, a FEAC code is validated when 8 out of the last 10 received codes are identical. The FEAC code is removed when 2 out of the last 10 received code do not match the validated code. When a logic 1 is written to AVC, a FEAC code is validated when 4 out of the last 5 received codes are identical. The FEAC code is removed when a single received FEACs does not match the validated code. IDLE: The IDLE bit enables the generation of an interrupt when a validated FEAC is removed. When a logic 1 is written to IDLE, the interrupt generation is enabled. |
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