PM7346 datasheet(289/419 Pages) PMC

289 / 419 page

PM7346 S/UNI-QJET

DATASHEET

PMC-960835

ISSUE 6

SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE 268

forced to logic 0. When FORCELOS is logic 0, the TPOS/TDATO[x] and

TNEG[x] outputs will operate normally.

LOC_RESET:

LOC_RESET performs a software local reset of the corresponding quadrant

of the S/UNI-QJET. When LOC_RESET is logic 1, the corresponding

quadrant of the S/UNI-QJET is held in a reset state. When LOC_RESET is

logic 0, the quadrant is in normal operational mode.

The LOC_RESET bit for quadrant 1 (reg 09BH) also resets the chip level

Utopia bus. While the LOC_RESET for quadrant 1 is set to logic 1, the QJETs

Utopia bus will be held in a reset state, and will not function. In applications

where the Utopia bus is required, the LOC_RESET for quadrant 1 should not

be permanently set to logic 1.

TCELL:

When the TCELL bit is a logic 1, the

TPOHFP/TFPO/TMFPO/TGAPCLK/TCELL[4:1] pin takes on the TCELL

function, and pulses once for every transmitted cell (idle or unassigned).

Reserved:

The reserved bit should be set to logic 0 for proper operation.

TPRBS:

the transmit stream in place of other payload data. The exact nature of the

PRBS is configurable through the PRGD registers (xA0H to xAFH).

Reserved:

The reserved bit should be set to logic 0 for proper operation.

AISOOF:

The AISOOF bit allows the receive data output stream on RDATO[x] to be

forced to all 1’s when the DS3, E3, or J2 FRMR loses frame. When AISOOF

is set to logic 1, RDATO[x] will be forced to all 1’s when frame alignment is

lost. When AISOOF is set to logic 0, RDATO[x] will continue to output raw

data even when frame alignment is lost.

Note that AISOOF is only valid in framer-only mode (FRMRONLY=1, S/UNI-

QJET Configuration 1 register).

PM7346 Datasheet(PDF) 289 Page - PMC-Sierra, Inc