PM7346 datasheet(119/419 Pages) PMC

119 / 419 page

PM7346 S/UNI-QJET

DATASHEET

PMC-960835

ISSUE 6

SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE 98

edge of RSCLK. When RSCLKR is a logic 0, the RDATO, RFPO/RMFPO,

and ROVRHD outputs are updated on the falling edge of RSCLK. If the

RXGAPEN bit is a logic 1, then RSCLKR affects RGAPCLK in the same

manner as it affects RSCLK.

LOFINT[1:0]

The LOFINT[1:0] bits determine the integration period used for asserting and

de-asserting E3 and DS3 Loss of Frame or J2 extended Loss of Frame on

the FRMLOF register bit of the S/UNI-QJET FRMR LOF Status register

(x9CH) and on the FRMSTAT[4:1] output pins (if this function is enabled by

the STATSEL[2:0] register bits of the S/UNI-QJET Configuration 2 Register).

The integration times are selected as follows:

Table 5

- LOF[1:0] Integration Period Configuration

LOFINT[1:0]

Integration Period

3ms

2ms

1ms

Reserved

RFRM[1:0]:

The RFRM[1:0] bits determine the expected frame structure of the received

signal according to the following table:

Table 6

- RFRM[1:0] Receive Frame Structure Configurations

RFRM[1:0]

Expected Receive Frame Structure

DS3 (C-bit parity or M23 depending on the setting of the CBE bit

in the DS3 FRMR Configuration register)

E3 (G.751 or G.832 depending on the setting of the

FORMAT[1:0] bits in the E3 FRMR Framing Options register)

J2 (G.704 and NTT compliant framing format)

PM7346 Datasheet(PDF) 119 Page - PMC-Sierra, Inc