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PM7346 Datasheet(PDF) 181 Page - PMC-Sierra, Inc |
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PM7346 Datasheet(HTML) 181 Page - PMC-Sierra, Inc |
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181 / 419 page ![]() PM7346 S/UNI-QJET DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3 PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE 160 Register 035H, 135H, 235H, 335H: DS3 TRAN Diagnostic Bit Type Function Default Bit 7 R/W DLOS 0 Bit 6 R/W DLCV 0 Bit 5 Unused X Bit 4 R/W DFERR 0 Bit 3 R/W DMERR 0 Bit 2 R/W DCPERR 0 Bit 1 R/W DPERR 0 Bit 0 R/W DFEBE 0 DFEBE: The DFEBE bit controls the insertion of far end block errors in the DS3 stream. When DFEBE is written with a logic 1, and the C-bit parity application is enabled, the three C-bits in M-subframe 4 are set to a logic 0. When DFEBE is written with a logic 0, FEBEs are indicated based on receive framing bit errors and path parity errors. DPERR: The DPERR bit controls the insertion of parity errors (P-bit errors) in the DS3 stream. When DPERR is written with a logic 1, the P-bits are inverted before insertion. When DPERR is written with a logic 0, the parity is calculated and inserted normally. DCPERR: The DCPERR bit controls the insertion of path parity errors in the DS3 stream. When DCPERR is written with a logic 1 and the C-bit parity application is enabled, the three C-bits in M-subframe 3 are inverted before insertion. When DCPERR is written with a logic 0, the path parity is calculated and inserted normally. DMERR: The DMERR bit controls the insertion of M-bit framing errors in the DS3 stream. When DMERR is written with a logic 1, the M-bits are inverted before insertion. When DMERR is written with a logic 0, the M-bits are inserted normally. |
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