PM7346 datasheet(193/419 Pages) PMC

193 / 419 page

PM7346 S/UNI-QJET

DATASHEET

PMC-960835

ISSUE 6

SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE 172

FEBEE is logic 0, changes in state of the FEBE bit does not cause an

interrupt on INTB.

FERFE:

The FERFE bit is an interrupt enable. When FERFE is logic 1, an interrupt is

generated on the INTB output when the Far End Receive Failure indication bit

(bit 1 of the G.832 Maintenance and Adaptation byte), or when the Remote

Alarm indication bit (bit 11 of the frame in G.751) changes state after the

selected persistency check is applied. When FERFE is logic 0, changes in

state of the FERF or RAI bit does not cause an interrupt on INTB.

AISDE:

The AISDE bit is an interrupt enable. When AISDE is logic 1, an interrupt is

generated on the INTB output when the AISD indication changes state.

When AISDE is logic 0, changes in state of the AISD signal does not cause

an interrupt on INTB.

PERRE:

The PERRE bit is an interrupt enable. When PERRE is logic 1, an interrupt is

generated on the INTB output when a BIP-8 error (in G.832 mode) is

detected. When PERRE is logic 0, occurrences of BIP-8 errors do not cause

an interrupt on INTB.

FERRE:

The FERRE bit is an interrupt enable. When FERRE is logic 1, an interrupt is

generated on the INTB output when a framing bit error is detected. When

FERRE is logic 0, occurrences of framing bit errors do not cause an interrupt

on INTB.

PM7346 Datasheet(PDF) 193 Page - PMC-Sierra, Inc