PM7346 datasheet(195/419 Pages) PMC

195 / 419 page

PM7346 S/UNI-QJET

DATASHEET

PMC-960835

ISSUE 6

SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3

PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE 174

the state of the FEBE bit has occurred since the last time this register was

read.

FERFI:

The FERFI bit is a transition indication. When FERFI is logic 1, a change of

state of the Far End Receive Failure indication bit (bit 1 of the G.832

Maintenance and Adaptation byte), or when the Remote Alarm indication bit

(bit 12 of the frame in G.751) has occurred. When FERFI is logic 0, no

changes in the state of the FERF or RAI bit has occurred since the last time

this register was read.

AISDI:

The AISDI bit is a transition indication. When AISDI is logic 1, a change in

state of the AISD indication has occurred. When AISDI is logic 0, no changes

in the state of the AISD signal has occurred since the last time this register

was read.

PERRI:

The PERRI bit is an event indication. When PERRI is logic 1, the occurrence

of one or more BIP-8 errors (in G.832 mode) has been detected. When

PERRI is logic 0, no occurrences of BIP-8 errors have occurred since the last

time this register was read.

FERRI:

The FERRI bit is an event indication. When FERRI is logic 1, the occurrence

of one or more framing bit error has been detected. When FERRI is logic 0,

no occurrences of framing bit errors have occurred since the last time this

The transition/event interrupt indications within this register work independently

from the interrupt enable bits, allowing the microprocessor to poll the register to

determine the activity of the maintenance events. The contents of this register

are cleared to logic 0 after the register is read; the INTB output is also cleared to

logic 1 if the interrupt was generated by any of the Maintenance Event outputs.

PM7346 Datasheet(PDF) 195 Page - PMC-Sierra, Inc