CP2201 datasheet(49/108 Pages) SILABS

49 / 108 page

CP2200/1

Rev. 1.0

11.5. Transmit Status and Control Registers

The CP2200 transmit interface is controlled and managed through the registers in Table 14. After each packet is

transmitted, information about the last transmitted packet can be obtained from the 52-bit transmit status vector

accessible through the TXSTA0 — TXSTA6 registers. The transmit status vector is described in Table 15.

Table 14. Transmit Status and Control Register Summary

Long Name

Address

Description

TXCN

Transmit Control

0x53

Contains the transmit configuration option over-

ride bits and the TXGO bit used to start packet

transmission.

TXBUSY

Transmit Busy Indicator

0x54

Read-only register returning 0x01 when transmit

interface is currently transmitting a packet and

0x00 when transmit interface is not transmitting.

TXPAUSEH

TXPAUSEL

Transmit Pause High and Low Bytes

0x55

0x56

16-bit pause value used for PAUSE packet

transmission. The pause value is in units of 512

bit times (51.2

μs).

TXSTARTH

TXSTARTL

Transmit Data Starting Address High

and Low Bytes

0x59

0x5A

Starting address of outgoing packet in the trans-

mit buffer. Packets added to the transmit buffer

must start at 0x0000.

TXENDH

TXENDL

Transmit Data Ending Address High

and Low Bytes

0x57

0x58

Address of last byte added to the transmit

buffer. This register is managed by hardware.

TXAUTOWR Transmit Data AutoWrite

0x03

Writes to this register add a byte to the transmit

buffer, set TXEND to the address of the written

byte, and increment TXSTART.

TXSTA6

TXSTA5

TXSTA4

TXSTA3

TXSTA2

TXSTA1

TXSTA0

Transmit Status Vector

0x5C

0x5D

0x5E

0x5F

0x60

0x61

0x62

52-bit transmit status vector containing informa-

tion about the last transmitted packet including

collision count, successful transmission, total

bytes transmitted, etc.

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