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CP2201 Datasheet(PDF) 40 Page - Silicon Laboratories |
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CP2201 Datasheet(HTML) 40 Page - Silicon Laboratories |
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40 / 108 page  CP2200/1 40 Rev. 1.0 9.5. Software Reset The software reset provides the host CPU the ability to reset the CP2200/1 through the parallel host interface. Writing a ‘1’ to RESET (SWRST.2) will force the device to enter the reset state with the exception that the external oscillator will not be stopped. As soon as the device enters the reset state, it will immediately exit the reset state and start device calibration; the Oscillator Initialization Complete interrupt is not be generated. After Self Initialization is complete, the device is fully functional. Note: The software reset is enabled after every reset; however, it may be de-selected as a reset source (see the register description for RSTEN on page 42). Register 12. SWRST: Software Reset Register Bits 7–3: UNUSED. Read = 00000b, Write = don’t care. Bit 2: RESET: Software Reset Initiate Writing a ‘1’ to this bit will generate a software reset. Bits 1–0: UNUSED. Read = 00b, Write = don’t care. R\W R\W R/W R/W R/W W R/W R/W Reset Value — — — — — RESET — — 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x75 |
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